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參數資料
| 型號： | IC61C1024L-25KI |
| 英文描述： | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 128K的× 8高速CMOS靜態(tài)RAM |
| 文件頁數： | 8/11頁 |
| 文件大?。?/td> | 204K |
| 代理商： | IC61C1024L-25KI |
IC61C1024
IC61C1024L
8
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
WRITE CYCLE SWITCHING CHARACTERISTICS
(1,2)
(Over Operating Range, Standard and Low
Power)
-12 ns
(3)
Min.
-15 ns
Min.
-20 ns
Min.
-25 ns
Min.
Symbol
t
WC
t
SCE
1
t
SCE
2
t
AW
t
HA
t
SA
t
PWE
(4)
t
SD
t
HD
t
HZWE
(5)
t
LZWE
(5)
Parameter
Max.
Max.
Max.
Max.
Unit
Write Cycle Time
12
—
15
—
20
—
25
—
ns
CE1
to Write End
10
—
12
—
15
—
20
—
ns
CE2 to Write End
10
—
12
—
15
—
20
—
ns
Address Setup Time to Write End
10
—
12
—
15
—
20
—
ns
Address Hold from Write End
0
—
0
—
0
—
0
—
ns
Address Setup Time
0
—
0
—
0
—
0
—
ns
WE
Pulse Width
10
—
10
—
12
—
15
—
ns
Data Setup to Write End
7
—
8
—
10
—
12
—
ns
Data Hold from Write End
0
—
0
—
0
—
0
—
ns
WE
LOW to High-Z Output
—
7
—
7
—
10
—
12
ns
WE
HIGH to Low-Z Output
2
—
2
—
2
—
2
—
ns
Notes:
1. Test conditions assume signal transition times of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V
and output loading specified in Figure 1.
2. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states to
initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced to the
rising or falling edge of the signal that terminates the Write.
3. -12 ns device for IC61C1024 only.
4. Tested with
OE
HIGH.
5. Tested with the load in Figure 2. Transition is measured ±500 mV from steady-state voltage. Not 100% tested.
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