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參數(shù)資料
| 型號(hào)： | IC61C1024-25KI |
| 英文描述： | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| 中文描述： | 128K的× 8高速CMOS靜態(tài)RAM |
| 文件頁數(shù)： | 9/11頁 |
| 文件大小： | 204K |
| 代理商： | IC61C1024-25KI |
IC61C1024
IC61C1024L
Integrated Circuit Solution Inc.
AHSR008-0B 10/18/2001
9
WRITE CYCLE NO. 2
(
OE
is HIGH During Write Cycle)
(1,2)
DATA UNDEFINED
LOW
t
WC
VALID ADDRESS
t
PWE1
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
OE
DATA
IN
VALID
t
LZWE
t
SD
Notes:
1. The internal write time is defined by the overlap of
CE1
LOW, CE2 HIGH and
WE
LOW. All signals must be in valid states
to initiate a Write, but any one can go inactive to terminate the Write. The Data Input Setup and Hold timing are referenced
to the rising or falling edge of the signal that terminates the Write.
2. I/O will assume the High-Z state if
OE
= V
IH
.
DATA UNDEFINED
t
WC
VALID ADDRESS
t
SCE
t
PWE1
t
PWE2
t
AW
t
HA
HIGH-Z
t
HD
t
SA
t
HZWE
ADDRESS
CE
WE
D
OUT
D
IN
DATA
IN
VALID
t
LZWE
t
SD
AC WAVEFORMS
WRITE CYCLE NO. 1
(
CE
Controlled,
OE
is HIGH or LOW)
(1 )
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC61C1024-25T | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IC61C1024-25TI | RES CH 68.1 EW 1% |
| IC61C1024L | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IC61C1024L-12HI | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IC61C1024L-15H | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC61C1024-25T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IC61C1024-25TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IC61C1024L | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IC61C1024L-12HI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IC61C1024L-15H | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:128K x 8 HIGH-SPEED CMOS STATIC RAM |
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