- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄360719 > IC43R32400-4B 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM PDF資料下載
參數(shù)資料
| 型號： | IC43R32400-4B |
| 英文描述： | 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| 中文描述： | 100萬× 32位× 4個銀行（128兆位）DDR SDRAM內(nèi)存 |
| 文件頁數(shù)： | 12/18頁 |
| 文件大小： | 3877K |
| 代理商： | IC43R32400-4B |
IC43R32400
12
Integrated Circuit Solution Inc.
DDR003-0B 11/10/2004
Electrical Characteristics and Recommended A.C. Operating Conditions
Symbol Parameter
Min Man Min Max
4.0 5.0 Unit
CL = 3
4 10
5 10
ns
t
CK
Clock cycle time
CL = 4
4 10
5
10
CL = 5
4 5 5
10
0.55
t
CK
0.55
t
CK
t
CH
t
CL
t
DQSCK
t
AC
t
DQSQ
t
RPRE
t
RPST
t
DQSS
t
WPRES
t
WPREH
t
WPST
t
DQSH
t
DQSL
t
IS
t
DS
t
DH
Clock high level width
0.45 0.55
0.45
Clock low level width
0.45
0.55
0.45
DQS-out access time from CK,CK#
-0.7 0.7
-0.7 0.7
ns
ns
Output access time from CK,CK#
-0.7 0.7
-0.7 0.7
DQS-DQ Skew
-
0.4
-
0.45
ns
Read preamble
0.9
1.1
0.9
1.1
t
CK
t
CK
Read postamble
0.4
0.6
0.4
0.6
1.15
t
CK
CK to valid DQS-in
0.85
1.15
0.85
DQS-in setup time
0
-
0
-
ns
ns
t
CK
t
CK
t
CK
ns
ns
ns
DQS-in hold time
0.35
- 0.35 -
DQS write postamble
0.4
0.6
0.4
0.6
DQS in high level pulse width
0.4
0.6
0.4
0.6
DQS in low level pulse width
0.4
0.6
0.4
0.6
Address and Control input setup time
0.9
-
1.0
-
DQ & DM setup time to DQS
0.45
-
0.5
-
DQ & DM hold time to DQS
0.45
-
tCLMIN
0.5
-
tCLMIN
t
HP
Clock half period
or
-
or
-
ns
tCHMIN
tCHMIN
t
QH
Output DQS valid window
tHP- - tHP - -
0.45 0.5
ns
t
RC
t
RFC
t
RAS
t
RCDRD
t
RCDWR
t
RP
t
RRD
tw
R
Row cycle time
15
-
12
-
t
CK
t
CK
Refresh row cycle time
17
-
14
-
100K
t
CK
Row active time
10
100K
8
RAS# to CAS# Delay in Read
5
-
4
-
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
t
CK
RAS# to CAS# Delay in Write
3
-
2
-
Row precharge time
3
-
3
-
Row active to Row active delay
3
-
2
-
Write recovery time
3
-
2
-
t
CDLR
Last data in to Read command 2 -
t
CCD
Col. Address to Col. Address delay
t
MRD
Mode register set cycle time
t
DAL
Auto precharge write recovery + Precharge
t
XSA
Self refresh exit to read command delay
2
-
1
-
1
-
2
-
2
-
8
-
7
-
200
-
200
-
t
PDEX
Power down exit time
tIS + 2tCK
-
tIS + 2tCK
-
ns
t
REF
Refresh interval time -
7.8
7.8
us
(VDD = 2.5V
+/-
5%, Ta = 0~70
°
C)
相關PDF資料 |
PDF描述 |
|---|---|
| IC43R32400-4BG | 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC43R32400-5B | 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC43R32400-5BG | 1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC61C1024L-25JI | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
| IC61C1024L-25K | 128K x 8 HIGH-SPEED CMOS STATIC RAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IC43R32400-4BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC43R32400-5B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC43R32400-5BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) DDR SDRAM |
| IC440A | 制造商:Black Box Corporation 功能描述:CONNECTORS, IN-LINE |
| IC441A-R2 | 制造商:Black Box Corporation 功能描述:VIDEO STEREO AUDIO BALUN |
發(fā)布緊急采購，3分鐘左右您將得到回復。