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IC42S32400
IC42S32400L
54
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005
Figure 19.2.Full Page Write Cycle (Burst Length=Full Page,CAS#Latency=2)
T0
T 1 T2
T3
T4
T5
T6
T7
T8
T9
T10 T 11 T12 T13 T14 T15 T16 T17 T18 T19 T20 T21 T22
RAx
RAx
CBx
RBx
CAx
RBy
RBy
t
CK2
RBx
DAx
DAx+1 DAx+2 DAx+3
DAx-1
DAx
DAx+1
DBx
DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6
CLK
CKE
CS#
RAS#
CAS#
WE#
BS0,1
A10
A0-A9
DQM
DQ
Hi-Z
Write
Command
Bank A
Activate
Command
Bank A
Write
Command
Bank B
Full Page burst operation does
not terminate when the burst
length is satisfied; the burst counter
increments and continues bursting
beginning with the starting address.
Activate
Command
Bank B
Activate
Command
Bank B
Precharge
Command
Bank B
High
Burst Stop
Command
Data is ignored
The burst counter wraps
from the highest order
page address back to zero
during this time interval