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參數(shù)資料
| 型號： | IC42S32400L-6TI |
| 英文描述： | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| 中文描述： | 100萬× 32位× 4個銀行（128兆）內(nèi)存 |
| 文件頁數(shù)： | 17/62頁 |
| 文件大小： | 899K |
| 代理商： | IC42S32400L-6TI |
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IC42S32400
IC42S32400L
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005
17
Data n
0
1
2
3
4
5
6
7
-
255
256
257
-
Column Address
n
n+1
n+2
n+3
n+4
n+5
n+6
n+7
-
n+255
n
n+1
-
2 words:
Burst Length
4 words:
8 words:
Full Page: Column address is repeated until terminated.
Data n
Data 0
Data 1
Data 2
Data 3
Data 4
Data 5
Data 6
Data 7
Column Address
A4
A4
A4
A4
A4
A4
A4
A4
Burst Length
A7
A7
A7
A7
A7
A7
A7
A7
A6
A6
A6
A6
A6
A6
A6
A6
A5
A5
A5
A5
A5
A5
A5
A5
A3
A3
A3
A3
A3
A3
A3
A3
A2
A2
A2
A2
A2#
A2#
A2#
A2#
A1
A1
A1#
A1#
A1
A1
A1#
A1#
A0
A0#
A0
A0#
A0
A0#
A0
A0#
4 words
8 words
The Burst Type can be one of two modes,Interleave Mode or Sequential Mode.
Burst Type Field (A3)
—Addressing Sequence of Sequential Mode
An internal column address is performed by increasing the address from the column address which is input to the
device.The internal column address is varied by the Burst Length as shown in the following table.When the value
of column address,(n +m),in the table is larger than 255,only the least significant 8 bits are effective.
A column access is started in the input column address and is performed by inverting the address
bits in the sequence shown in the following table.
Addressing Sequence of Interleave Mode
This field specifies the number of clock cycles from the assertion of the Read command to the first
read data.The minimum whole value of CAS#Latency depends on the frequency of CLK.The
minimum whole value satisfying the following formula must be programmed into this field.
t
CAC
(min)<=CAS#Latency X t
CK
CAS#Latency Field (A6~A4)
A6
0
0
0
0
1
A5
0
0
1
1
X
A4
0
1
0
1
X
CAS#Latency
Reserved
Reserved
2 clocks
3 clocks
Reserved
A3
0
1
Burst Type
Sequential
Interleave
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IC42S32400L-6TIG | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7B | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7BG | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7BI | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7T | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S32400L-6TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7B | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7BI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400L-7BIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
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