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| 型號(hào)： | IC42S32400-7BG |
| 英文描述： | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| 中文描述： | 100萬× 32位× 4個(gè)銀行（128兆）內(nèi)存 |
| 文件頁數(shù)： | 6/62頁 |
| 文件大?。?/td> | 899K |
| 代理商： | IC42S32400-7BG |
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IC42S32400
IC42S32400L
6
Integrated Circuit Solution Inc.
DR038-0C 02/01/2005
Operation Mode
Fully synchronous operations are performed to latch the commands at the positive edges of CLK.Table 2 shows the truth
table for the operation commands.
Table 2.Truth Table (Note (1),(2))
Note:
1. V =Valid,X =Don ’t care,L =Logic low,H =Logic high
2. CKEn signal is input level when commands are provided.
CKEn-1 signal is input level one clock cycle before the commands are provided.
3. These are states of bank designated by BS signal.
4. Device state is 1,2,4,8,and full page burst operation.
5. Power Down Mode can not enter in the burst operation.
When this command is asserted in the burst cycle,device state is clock suspend mode.
6. DQM0-3
Command
BankActivate
BankPrecharge
PrechargeAll
Write
Write and Auto Precharge Active
(3)
State
Idle
(3)
Any
Any
Active
(3)
CKEn-1 CKE
H
H
H
H
H
DQM
(6)
X
X
X
X
X
BS0,1
V
V
X
V
V
A10
Row address
L
H
L
H
(A0 ~A7)
A11,A9-0
CS# RAS# CAS# WE#
L
L
L
L
L
L
L
H
L
H
X
X
X
X
X
H
H
H
L
L
H
L
L
L
L
X
X
Read
Read and Autoprecharge
Active
(3)
Active
(3)
H
H
X
X
X
X
V
V
L
H
L
H
H
L
L
H
H
L
Mode Register
No-Operation
Burst Stop
Device Deselect
AutoRefresh
SelfRefresh Entry
SelfRefresh Exit
Set Idle
Any
Active
(4)
Any
Idle
Idle
Idle
(SelfRefresh)
H
H
H
H
H
H
L
X
X
X
X
H
L
H
X
X
X
X
X
X
X
OP code
X
X
X
X
X
X
L
L
L
H
L
L
H
L
X
H
L
X
H
L
X
X
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
L
H
H
X
L
L
X
H
X
X
H
X
X
H
X
X
L
H
L
X
H
H
X
H
X
X
H
X
X
H
X
X
X
X
X
X
X
X
X
X
X
X
X
X
Clock Suspend Mode Entry Active
Power Down Mode Entry
H
H
L
L
X
X
X
X
X
X
X
X
Any
(5)
Clock Suspend Mode Exit
Power Down Mode Exit
Active
Any
(PowerDown)
Active
L
L
H
H
X
X
X
X
X
X
X
X
Data Write/Output Enable
Data Mask/Output Disable Active
H
H
X
X
L
H
X
X
X
X
X
X
Column
address
Column
address
(A0 ~A7)
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| IC42S32400-7BI | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-7T | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-7TG | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-7TI | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-8B | 1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S32400-7BI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-7BIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-7T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-7TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
| IC42S32400-7TI | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:1M x 32 Bit x 4 Banks (128-MBIT) SDRAM |
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