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參數(shù)資料
| 型號： | IC42S16102-6TI |
| 英文描述： | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| 中文描述： | 為512k × 16位× 2銀行（16兆）內存 |
| 文件頁數(shù)： | 33/78頁 |
| 文件大小： | 790K |
| 代理商： | IC42S16102-6TI |
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IC42S16102
Integrated Circuit Solution Inc.
DR042-0A 01/18/2005
33
Write Cycle (Full Page) Interruption Using
the Burst Stop Command
The IC42S16102 can input data continuously from the
burst start address (a) to location a+255 during a write
cycle in which the burst length is set to full page. The
IC42S16102 repeats the operation starting at the 256th
cycle with data input returning to location (a) and continuing
with a+1, a+2, a+3, etc. A burst stop command must be
executed to terminate this cycle. A precharge command
must be executed with in the ACT to PRE command period
(t
RAS
max.) following the burst stop command. After the
period (t
WBD
) required for burst data input to stop following
the execution of the burst stop command has elapsed, the
write cycle terminates. This period (t
WBD
) is zero clock
cycles, regardless of the
CAS
latency.
CAS
latency = 2, burst length = 4
READ A0
COMMAND
UDQM
LDQM
I/O8-I/O15
I/O0-I/O 7
CLK
D
OUT
A0
t
QMD=2
HI-Z
HI-Z
HI-Z
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
D
OUT
A2
D
OUT
A3
D
OUT
A1
D
OUT
A0
Burst Data Interruption Using the
U/LDQM Pins (Read Cycle)
Burst data output can be temporarily interrupted (masked)
during a read cycle using the U/LDQM pins. Regardless of
the
CAS
latency, two clock cycles (t
QMD
) after one of the U/
LDQM pins goes HIGH, the corresponding outputs go to
the HIGH impedance state. Subsequently, the outputs are
maintained in the high impedance state as long as that U/
LDQM pin remains HIGH. When the U/LDQM pin goes
LOW, output is resumed at a time t
QMD
later. This output
control operates independently on a byte basis with the
UDQM pin controlling upper byte output (pins
I/O8-I/O15) and the LDQM pin controlling lower byte output
(pins I/O0 to I/O7).
Since the U/LDQM pins control the device output buffers
only, the read cycle continues internally and, in particular,
incrementing of the internal burst counter continues.
CAS
latency = 2, 3, burst length = full page
WRITE A0
COMMAND
I/O
CLK
D
IN
A0
D
IN
A1
D
IN
A
D
IN
A1
D
IN
A2
t
WBD=0
t
RP
READ (CA=A, BANK 0)
BURST STOP
BST
PRE 0
INVALID DATA
PRECHARGE (BANK 0)
Don’t Care
相關PDF資料 |
PDF描述 |
|---|---|
| IC42S16102-6TIG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-7BG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-7BIG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-7T | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-7TG | 512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S16102-6TIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-7BG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-7BIG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-7T | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16102-7TG | 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
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