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| 型號(hào)： | IC42S16100-7TG |
| 英文描述： | 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| 中文描述： | 為512k × 16位× 2組（16兆）同步動(dòng)態(tài)RAM |
| 文件頁(yè)數(shù)： | 28/78頁(yè) |
| 文件大小： | 789K |
| 代理商： | IC42S16100-7TG |
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IC42S16100
28
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
Interval Between Write and Read Commands
A new read command can be executed while a write cycle
is in progress, i.e., before that cycle completes. Data
corresponding to the new read command is output after
the
CAS
latency has elapsed from the point the new read
command was executed. The I/On pins must be placed in
the HIGH impedance state at least one cycle before data
is output during this operation.
The interval (t
CCD
) between command must be at least one
clock cycle.
The selected bank must be set to the active state before
executing this command.
I/O
WRITE A0
READ B0
COMMAND
CLK
D
IN
A0
D
OUT
B0
D
OUT
B2
D
OUT
B1
D
OUT
B3
t
CCD
HI-Z
WRITE (CA=A, BANK 0)
READ (CA=B, BANK 0)
I/O
WRITE A0
READ B0
COMMAND
CLK
D
IN
A0
D
OUT
B0
D
OUT
B2
D
OUT
B1
D
OUT
B3
t
CCD
HI-Z
WRITE (CA=A, BANK 0)
READ (CA=B, BANK 0)
CAS
latency = 2, burst length = 4
CAS
latency = 3, burst length = 4
Don’t Care
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IC42S16100-7TI | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16100-7TIG | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM |
| IC42S16101 | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-5BG | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
| IC42S16101-5BIG | 制造商:ICSI 制造商全稱(chēng):Integrated Circuit Solution Inc 功能描述:512K x 16 Bit x 2 Banks (16-MBIT) SDRAM |
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