參數(shù)資料
型號(hào)： IC42S16100-5TI
英文描述： 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
中文描述： 為512k × 16位× 2組（16兆）同步動(dòng)態(tài)RAM
文件頁數(shù)： 24/78頁
文件大?。?/td> 789K
代理商： IC42S16100-5TI
IC42S16100
24
Integrated Circuit Solution Inc.
DR024-0D 06/25/2004
CAS
latency = 2,3, burst length = 4
CAS
latency = 2, burst length = 4
Burst Read
The read cycle is started by executing the read command.
The address provided during read command execution is
used as the starting address. First, the data corresponding
to this address is output in synchronization with the clock
signal after the
CAS
latency period. Next, data
corresponding
to an address generated automatically by the device is
output in synchronization with the clock signal.
The output buffers go to the LOW impedance state
CAS
latency minus one cycle after the read command, and go
to the HIGH impedance state automatically after the last
data is output. However, the case where the burst length
is a full page is an exception. In this case the output buffers
must be set to the high impedance state by executing a
burst stop command.
Note that upper byte and lower byte output data can be
masked independently under control of the signals applied
to the U/LDQM pins. The delay period (t
QMD
) is fixed at two,
regardless of the
CAS
latency setting, when this function
is used.
The selected bank must be set to the active state before
executing this command.
Burst Write
The write cycle is started by executing the command. The
address provided during write command execution is used
as the starting address, and at the same time, data for this
address is input in synchronization with the clock signal.
Next, data is input in other in synchronization with the clock
signal. During this operation, data is written to address
generated automatically by the device. This cycle terminates
automatically after a number of clock cycles determined by
the stipulated burst length. However, the case where the
burst length is a full page is an exception. In this case the
write cycle must be terminated by executing a burst stop
command. The latency for I/O pin data input is zero,
regardless of the
CAS
latency setting. However, a wait
period (write recovery: t
DPL
) after the last data input is
required for the device to complete the write operation.
Note that the upper byte and lower byte input data can be
masked independently under control of the signals applied
to the U/LDQM pins. The delay period (t
DMD
) is fixed at
zero, regardless of the
CAS
latency setting, when this
function is used.
The selected bank must be set to the active state before
executing this command.
READ A0
COMMAND
UDQM
LDQM
I/O8-I/O15
I/O0-I/O 7
CLK
D
OUT
A0
t
QMD=2
HI-Z
HI-Z
HI-Z
READ (CA=A, BANK 0)
DATA MASK (LOWER BYTE)
DATA MASK (UPPER BYTE)
D
OUT
A2
D
OUT
A3
D
OUT
A1
D
OUT
A0
BURST LENGTH
WRITE
COMMAND
I/O
CLK
D
IN
0
D
IN
1
D
IN
2
D
IN
3
相關(guān)PDF資料
PDF描述
IC42S16100-5TIG 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S16100-6T 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S16100-6TG 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S16100-6TI 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S16100-6TIG 512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
IC42S16100-5TIG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S16100-6T 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S16100-6TG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S16100-6TI 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
IC42S16100-6TIG 制造商:ICSI 制造商全稱:Integrated Circuit Solution Inc 功能描述:512K x 16 Bits x 2 Banks (16-MBIT) SYNCHRONOUS DYNAMIC RAM
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