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參數(shù)資料
| 型號(hào)： | IC41UV4105-70J |
| 英文描述： | 1Mx4 bit Dynamic RAM with Fast Page Mode |
| 中文描述： | 1Mx4位動(dòng)態(tài)RAM的快速頁(yè)面模式 |
| 文件頁(yè)數(shù)： | 6/17頁(yè) |
| 文件大?。?/td> | 193K |
| 代理商： | IC41UV4105-70J |
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IC41UV4105
6
Integrated Circuit Solution Inc.
DR020-0B 08/24/2001
ELECTRICAL CHARACTERISTICS
(1)
(Recommended Operating Conditions unless otherwise noted.)
Symbol
Parameter
Test Condition
Speed
Min.
5
Max.
Unit
I
IL
Input Leakage Current
Any input 0V
≤
V
IN
≤
Vcc
Other inputs not under test = 0V
5
μA
I
IO
Output Leakage Current
Output is disabled (Hi-Z)
0V
≤
V
OUT
≤
Vcc
I
OH
=
2.0 mA
5
5
μA
V
OH
Output High Voltage Level
2.0
V
V
OL
Output Low Voltage Level
I
OL
= 2 mA
0.8
V
I
CC
1
Standby Current: TTL
RAS
,
CAS
≥
V
IH
1
mA
I
CC
2
Standby Current: CMOS
RAS
,
CAS
≥
V
CC
0.2V
0.5
mA
I
CC
3
Operating Current:
Random Read/Write
(2,3,4)
Average Power Supply Current
RAS
,
CAS
,
Address Cycling, t
RC
= t
RC
(min.)
-50
-70
-100
75
65
55
mA
I
CC
4
Operating Current:
Fast Page Mode
(2,3,4)
Average Power Supply Current
RAS
= V
IL
,
CAS
≥
V
IH
t
RC
= t
RC
(min.)
-50
-70
-100
60
50
40
mA
I
CC
5
Refresh Current:
RAS
-Only
(2,3)
Average Power Supply Current
RAS
Cycling,
CAS
≥
V
IH
t
RC
= t
RC
(min.)
-50
-70
-100
75
65
55
mA
I
CC
6
Refresh Current:
CBR
(2,3,5)
Average Power Supply Current
RAS
,
CAS
Cycling
t
RC
= t
RC
(min.)
-50
-70
-100
75
65
55
mA
Notes:
1. An initial pause of 200 μs is required after power-up followed by eight
RAS
refresh cycles (
RAS
-Only or CBR) before proper device
operation is assured. The eight
RAS
cycles wake-up should be repeated any time the t
REF
refresh requirement is exceeded.
2. Dependent on cycle rates.
3. Specified values are obtained with minimum cycle time and the output open.
4. Column-address is changed once each Fast page cycle.
5. Enables on-chip refresh and address counters.
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