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| 型號： | IBM25PPC750L-GB500CA2ST |
| 英文描述： | Microprocessor |
| 中文描述： | 微處理器 |
| 文件頁數(shù)： | 18/50頁 |
| 文件大?。?/td> | 516K |
| 代理商： | IBM25PPC750L-GB500CA2ST |
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Page 14
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
5/20/99
PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
60x Bus Output AC Specifications
The following table provides the 60x bus output AC timing specifications for the 750 as defined in Figure 5.
Output timing specification for the L2 bus are provided in the Section “L2 Bus Output AC Specifications,” on
page 19.
60X Bus Output AC Timing Specifications for the 750
1
See Table “Recommended Operating Conditions,” on page 7 for operating conditions, C
L
= 50pF
2
Num
Characteristic
300, 333, 366, 400, 466 MHz
Unit
Notes
Minimum
Maximum
12
SYSCLK to Output Driven (Output Enable Time)
0.5
ns
8
13
SYSCLK to Output Valid (TS, ABB, ARTRY, DBB, and TBST)
–
4.5
ns
5
14
SYSCLK to all other Output Valid (all except TS, ABB, ARTRY,
DBB, and TBST)
–
5.0
ns
5
15
SYSCLK to Output Invalid (Output Hold)
(optional: L2_TSTCLK = GND)
1.0
1.2
ns
3, 8, 9
16
SYSCLK to Output High Impedance (all signals except ABB,
ARTRY, and DBB)
–
6.0
ns
8
17
SYSCLK to ABB and DBB high impedance after precharge
–
1.0
t
SYSCLK
4, 6, 8
18
SYSCLK to ARTRY high impedance before precharge
–
5.5
ns
8
19
SYSCLK to ARTRY precharge enable
0.2
×
t
SYSCLK
+ 1.0
ns
3, 4, 7
20
Maximum delay to ARTRY precharge
1
t
SYSCLK
4, 7
21
SYSCLK to ARTRY high impedance after precharge
2
t
SYSCLK
4, 7, 8
Note:
1. All output specifications are measured from the midpoint voltage (1.4V) of the rising edge of SYSCLK to the midpoint voltage of the signal in question.
Both input and output timings are measured at the pin.
2. All maximum timing specifications assume C
L
= 50pF.
3. This minimum parameter assumes CL = 0pF.
4. t
is the period of the external bus clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration of the parameter in question.
5. Output signal transitions from GND to 2.0V or OV
DD
to 0.8V.
6. Nominal precharge width for ABB and DBB is 0.5 t
SYSCLK
.
7. Nominal precharge width for ARTRY is 1.0 t
SYSCLK
.
8. Guaranteed by design and characterization, and not tested.
9. For extra output hold, L2_TSTCLK may be tied to ground. Otherwise L2_TSTCLK should be tied to OV
DD
.
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