參數(shù)資料
型號: IBM25PPC750L-GB400A2R
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 400 MHz, RISC PROCESSOR, CBGA360
封裝: 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360
文件頁數(shù): 30/48頁
文件大小: 608K
代理商: IBM25PPC750L-GB400A2R
Page 36
Version 1.02
12/8/99
PowerPC 740 and PowerPC 750 Microprocessor
CMOS 0.20
m Copper Technology, PID-8p, PPC740L and PPC750L, dd3.2
System Design Information
PLL Conguration
The 750 PLL is configured by the PLL_CFG[0:3] signals. For a given SYSCLK (bus) frequency, the PLL con-
figuration signals set the internal CPU and VCO frequency of operation.
PLL Conguration
PLL_CFG
(0:3)
Processor to Bus Frequency Ratio
VCO Divider5
bin
dec
0000
0
Rsv1
n/a
0001
1
7.5x
2
0010
2
7x
2
0011
3
PLL Bypass3
n/a
0100
4
2x6
2
0101
5
6.5x
2
0110
6
10x
2
0111
7
4.5x
2
1000
8
3x
2
1001
9
5.5x
2
1010
10
4x
2
1011
11
5x
2
1100
12
8x
2
1101
13
6x
2
1110
14
3.5x
2
1111
15
Off4
n/a
Note:
1. Reserved settings.
2. SYSCLK min is limited by the lowest frequency that manufacturing will support, see Section , “Clock AC Specifications,” for valid SYSCLK and VCO
frequencies.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for 1:1 mode
operation. This mode is intended for factory use only. Note: The AC timing specifications given in the document do not apply in PLL-bypass mode.
4. In Clock-off mode, no clocking occurs inside the 750 regardless of the SYSCLK input.
5. The VCO to core clock ratio is 2x for 740/750. This simplifies clock frequency calculations so the user can disregard the VCO frequency. The VCO will
operate correctly when the core clock is within specification.
6. Not tested.
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