參數(shù)資料
型號: IBM25PPC750L-GB333D2ST
英文描述: Microprocessor
中文描述: 微處理器
文件頁數(shù): 35/50頁
文件大?。?/td> 516K
代理商: IBM25PPC750L-GB333D2ST
5/20/99
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
Page 31
PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
RSRV
D3
Low
Output
SMI
A12
Low
Input
SRESET
E10
Low
Input
SYSCLK
H9
Input
TA
F1
Low
Input
TBEN
A2
High
Input
TBST
A11
Low
I/O
TCK
B10
High
Input
TDI
B7
High
Input
TDO
D9
High
Output
TEA
J1
Low
Input
TLBISYNC
A3
Low
Input
TMS
C8
High
Input
TRST
A10
Low
Input
TS
K7
Low
I/O
TSIZ0-TSIZ2
A9, B9, C9
High
Output
TT0-TT4
C10, D11, B12, C12, F11
High
I/O
WT
C3
Low
Output
VDD
2
G8, G10, G12, J8, J10, J12, L8, L10, L12, N8, N10, N12
VOLTDET
3
K13
High
Output
Pinout Listing for the 360 CBGA package (cont.)
Signal Name
Pin Number
Active
I/O
Note:
1. These are test signals for factory use only and must be pulled up to OV
DD
for normal machine operation.
2. OV
DD
inputs supply power to the I/O drivers and V
DD
inputs supply power to the processor core.
3. Internally tied to L2OV
DD
in the 750 360 CBGA package. This is NOT a supply pin.
4. These pins are reserved for potential future use as additional L2 address pins.
5. L2_TSTCLK may be tied to ground for normal machine operation, if extra 60x bus output hold is required on all 60x bus signals. See Table “60X Bus
Output AC Timing Specifications for the 750
1
,” on page 14, spec 15.
6. These pins are no connects on dd2.x and have no function. They will be added to dd3.x to select voltage levels for the L2 bus (A19) and the rest of the
I/O (W01). Leaving the pin unconnected will select the normal supply value. Connecting these pins to HRESET# or ground on dd3.x will select lower
voltage supply ranges.
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