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參數(shù)資料
| 型號： | IBM25PPC750L-FB0C400W |
| 元件分類： | 32位微控制器 |
| 英文描述： | 32-Bit Microprocessor |
| 中文描述： | 32位微處理器 |
| 文件頁數(shù)： | 42/50頁 |
| 文件大?。?/td> | 516K |
| 代理商： | IBM25PPC750L-FB0C400W |
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Page 38
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
5/20/99
PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
Pull-up Resistor Requirements
The 750 requires high-resistive (weak: 10K
) pull-up resistors on several control signals of the bus interface
to maintain the control signals in the negated state after they have been actively negated and released by the
750 or other bus masters. These signals are: TS, ABB, DBB, TT[0:4], TBST, GBL, and ARTRY.
In addition, the 750 has one open-drain style output that requires a pull-up resistor (weak or stronger: 4.7K
- 1- K
) if it is used by the system. This signal is: CKSTP_OUT.
The data bus input receivers are normally turned off when no read operation is in progress and do not require
pull-up resistors on the data bus. Other data bus receivers in the system, however, may require pull-ups, or
that those signals be otherwise driven by the system during inactive periods. The data bus signals are: DH[0-
31], DL[0-31], and DP[0-7].
If address or data parity is not used by the system, and the respective parity checking is disabled through
HID0, the input receivers for those pins are disabled, and those pins do not require pull-up resistors and
should be left unconnected by the system. If all parity generation is disabled through HID0, then all parity
checking should also be disabled through HID0, and all parity pins may be left unconnected by the system.
No pull-up resistors are normally required for the L2 interface.
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| IBM25PPC750L-GB300A2R | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:MICROPROCESSOR|32-BIT|CMOS|BGA|360PIN|CERAMIC |
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