參數(shù)資料
型號(hào)： IBM25PPC750L-FB0B375W
元件分類： 32位微控制器
英文描述： 32-Bit Microprocessor
中文描述： 32位微處理器
文件頁(yè)數(shù)： 23/50頁(yè)
文件大?。?/td> 516K
代理商： IBM25PPC750L-FB0B375W
5/20/99
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
Page 19
PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
L2 Bus Output AC Specifications
The following table provides the L2 bus output interface AC timing specifications for the 750 as defined in
Figure 8.
L2 Bus Output Interface AC Timing Specifications
1
See Table “Recommended Operating Conditions,” on page 7 for operating conditions, C
L
= 20pF
3
Num
Characteristic
L2CR[14-15] is equivalent to:
Unit
Notes
00
2
01
10
11
Min
Max
Min
Max
Min
Max
Min
Max
26
L2SYNC_IN to output valid, 300,
333, 366 MHz processor sorts.
—
3.2
—
3.7
—
Rsv
5
—
Rsv
5
ns
26
L2SYNC_IN to output valid, 400
MHz processor sort.
—
3.0
—
3.5
—
Rsv
5
—
Rsv
5
ns
26
L2SYNC_IN to output valid, 466
MHz processor sort.
—
2.6
—
3.1
—
Rsv
5
—
Rsv
5
ns
27
L2SYNC_IN to output hold
0.5
—
1.0
—
Rsv
5
—
Rsv
5
—
ns
4,6
28
L2SYNC_IN to high impedance
—
3.0
—
4.0
—
Rsv
5
—
Rsv
5
ns
6
Note:
1. All outputs are measured from the midpoint voltage (1.4v) of the rising edge of L2SYNC_IN to the midpoint voltage of the signal in question. The output
timings are measured at the pins.
2. The outputs are valid for both single-ended and differential L2CLK modes. For flow-through and pipelined reg-reg synchronous burst SRAMs,
L2CR[14-15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14-15] = 01 is recommended.
3. All maximum timing specifications assume CL = 20pF.
4. This measurement assumes CL= 5pF.
5. Reserved for future use.
6. Guaranteed by design and characterization, and not tested.
Figure 8. L2 Bus Output Timing Diagrams
27
VM
VM = Midpoint Voltage (1.4V)
L2SYNC_IN
26
ALL OUTPUTS
VM
28
L2DATA BUS
VM
VM
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