參數(shù)資料
型號(hào)： IBM25PPC750GXEBR5042T
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 933 MHz, RISC PROCESSOR, CBGA292
封裝： 21 X 21 MM, 1 MM PITCH, LEAD FREE, CERAMIC, BGA-292
文件頁(yè)數(shù)： 46/74頁(yè)
文件大?。?/td> 1054K
代理商： IBM25PPC750GXEBR5042T
Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
System Design Information
Page 50 of 73
750GX_ds_body.fm SA14-2765-02
September 2, 2005
5.3 PLL Power Supply Filtering
The 750GX microprocessor has two separate AVDD signals (A1VDD and A2VDD), which provide power to the
clock generation PLL.
Most designs are expected to use a single PLL configuration mode throughout the application. These types of
designs should use the default PLL (PLL0), filtering its respective supply, A1VDD. The A2VDD supply signal
should be grounded through a 100
resistor, as shown in Figure 5-1 on page 51.
For designs planning to optimize power savings through dynamic switching between dual PLL circuits, it is
recommended, though not required, that each AVDD have a separate voltage input and filter circuit. This
optional circuit is also shown.
To ensure stability of the internal clock, the power supplied to the AVDD input signals should be filtered using
a circuit similar to the one shown in Figure 5-1 on page 51. The circuit should be placed as close as possible
to the AVDD pin to ensure it filters out as much noise as possible.
For descriptions of the sample PLL power supply filtering circuits, see Table 5-3.
Table 5-3. Sample PLL Power Supply Filtering Circuits
Circuit Description
Number of
Filtering
Circuits
Ferrite
Beads
Circuit Figure
Recommended
Circuit Design
Notes
Single PLL circuit configuration that uses the A1VDD
and ties the A2VDD pin to GND.
11
Yes
Single PLL circuit configuration that uses both the
A1VDD and the A2VDD pins and a single ferrite bead.
11
Optional
Dual PLL configuration that uses a separate circuit
for the A1VDD pin and for the A2VDD pin.
22
Yes
Notes:
1. Optional configurations are supported, though not recommended.
2. This circuit design can be used with the dual PLL feature enabled, though optimum power savings may not be realized.
3. This circuit design can be used with the dual PLL feature enabled to optimize power savings.
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