參數(shù)資料
型號(hào)： IBM25PPC750GXEBB2H33T
元件分類： 微控制器/微處理器
英文描述： 32-BIT, 800 MHz, RISC PROCESSOR, CBGA292
封裝： 21 X 21 MM, 1 MM PITCH, CERAMIC, BGA-292
文件頁(yè)數(shù)： 44/74頁(yè)
文件大?。?/td> 1054K
代理商： IBM25PPC750GXEBB2H33T
Datasheet
IBM PowerPC 750GX RISC Microprocessor
DD1.X
750GX_ds_body.fm SA14-2765-02
September 2, 2005
System Design Information
Page 49 of 73
01101
13
6.5×
77
154
500
1000
01110
14
7×
71
143
500
1000
01111
15
7.5×
67
133
500
1000
10000
16
8×
62
125
500
1000
10001
17
8.5×
59
118
500
1000
10010
18
9×
55
111
500
1000
10011
19
9.5×
51
105
500
1000
10100
20
10×
50
100
500
1000
10101
21
11×
45
91
500
1000
10110
22
12×
42
83
500
1000
10111
23
13×
38
77
500
1000
11000
24
14×
36
71
500
1000
11001
25
15×
33
66
500
1000
11010
26
16×
31
63
500
1000
11011
27
17×
29
59
500
1000
11100
28
18×
28
56
500
1000
11101
29
19×
26
53
500
1000
11110
30
20×
25
50
500
1000
11111
31
Off2
N/A
Table 5-2. 750GX Microprocessor PLL Configuration (Continued)
PLL_CFG [0:4]
Processor to Bus
Frequency Ratio
(PTBFR)
Frequency Range Supported by VCO Having an Example Range of...
SYSCLK1 (MHz)
Core (MHz)
Binary
Decimal
Minimum
(SYSCLKMIN)
Maximum
(SYSCLKMAX)
Minimum
(Core FrequencyMIN)
Maximum
(Core FrequencyMAX)
Notes:
1. The SYSCLK frequency equals the core frequency divided by the processor-to-bus frequency ratio (PTBFR).
2. In clock-off mode, no clocking occurs inside the 750GX regardless of the SYSCLK input.
3. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set
for 1:1 mode operation. This mode is intended for factory use only.
The AC timing specifications given in the document do not apply in PLL-bypass mode.
4. The 2×–3.5× processor-to-bus ratios are currently not supported when miss-under-miss is enabled (HID0(14) = '1').
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