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參數資料
| 型號： | IBM25PPC750CXEJQ7022T |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 600 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 27 X 27 MM, LEAD FREE, PLASTIC, BGA-256 |
| 文件頁數： | 10/44頁 |
| 文件大?。?/td> | 416K |
| 代理商： | IBM25PPC750CXEJQ7022T |
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Data Sheet
PowerPC 750CXe RISC Microprocessor
Preliminary
Electrical and Thermal Characteristics
Page 10 of 36
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
4.2 AC Electrical Characteristics
This section provides the AC electrical characteristics for the PowerPC 750CXe. After fabrication, parts are
sorted by maximum processor core frequency as shown in the Section 4.2.1 on Page 10, and tested for
conformance to the AC specifications for that frequency. The processor core frequency is determined by the
bus (SYSCLK) frequency and the settings of the PLL_CFG(0-3) signals.
4.2.1 Clock AC Specifications
Table 4-6 provides the clock AC timing specifications as defined in Figure 4-1.
Table 4-6. Clock AC Timing Specifications1,6 See Table 4-2 on page 7, for recommended operating conditions.
Num
Characteristic
Value
Unit
Notes
Min
Max
Processor frequency
400
600
MHz
6
SYSCLK frequency
40
133
MHz
1
SYSCLK cycle time
7.5
32
ns
2, 3
SYSCLK rise and fall time (slew rate)
1.0
4.0
V/ns
2, 3
4
SYSCLK duty cycle measured at 0.8 V
25
75
%
3
SYSCLK jitter
–
±150
ps
4, 3
Internal PLL relock time
–
100
s5
Notes:
1. Caution: The SYSCLK frequency and the PLL_CFG[0:3] settings must be chosen such that the resulting SYSCLK (bus) frequency and CPU (core)
frequency do not exceed their respective maximum or minimum operating frequencies. Refer to the PLL_CFG[0:3] signal description in Section 6.1
“PLL Configuration,” on page 26 for valid PLL_CFG[0:3] settings.
2. Rise and fall times for the SYSCLK input are measured from +0.4 to +1.2 V.
3. Timing is guaranteed by design and characterization, and is not tested.
4. The total input jitter (short term and long term combined) must be under
±150ps. Contact IBM for use with spread-spectrum clocks or clocks with jitter
in excess of
±150ps.
5. Relock timing is guaranteed by design and characterization, and is not tested. PLL-relock time is the maximum amount of time required for PLL lock
after a stable VDD and SYSCLK are reached during the power-on reset sequence. This specification also applies when the PLL has been disabled
and subsequently re-enabled during sleep mode. Also note that HRESET must be held asserted for a minimum of 255 bus clocks after the PLL-relock
time during the power-on reset sequence.
6. Contact IBM for operation at core frequencies below 400MHz.
Figure 4-1. SYSCLK Input Timing Diagram
VM
CV
IL
CV
IH
1
2
4
3
4
SYSCLK
VM - Midpoint Voltage (+0.8V)
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| IBM25PPC750FL-GR0123V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
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