參數(shù)資料
型號: IBM25PPC750CXEJP5512T
元件分類: 微控制器/微處理器
英文描述: 32-BIT, 533 MHz, RISC PROCESSOR, PBGA256
封裝: 27 X 27 MM, PLASTIC, BGA-256
文件頁數(shù): 28/44頁
文件大?。?/td> 416K
代理商: IBM25PPC750CXEJP5512T
Data Sheet
PowerPC 750CXe RISC Microprocessor
Preliminary
System Design Information
Page 26 of 36
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
6. System Design Information
This section provides electrical and thermal design recommendations for successful application of the
PowerPC 750CXe.
6.1 PLL Configuration
PLL-CFG (Table 6-1) must be set so that both SYSCLK and the core frequency are within the Clock AC
Timing Specifications shown in Table 4-6 on page 10. In addition, the core frequency must not exceed the
limit specified in the part number and the system must meet the required specifications.
Table 6-1. PowerPC 750CXe Microprocessor PLL Configuration
PLL_CFG (0:3)
Processor to Bus Frequency Ratio (r)
Bin
Dec
0000
0
2.5x1
0001
1
7.5x
0010
2
7x
0011
3
PLL Bypass2
0100
4
2x1
0101
5
6.5x
0110
6
9x5
10x
0111
7
4.5x
1000
8
3x
1001
9
5.5x
1010
10
4x
1011
11
5x
1100
12
8x
1101
13
6x
1110
14
3.5x
1111
15
Off3
Notes:
1. The 2X and 2.5X Processor to Bus Ratios are currently not supported.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set
for 1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in the document do
not apply in PLL-bypass mode.
3. In Clock - off mode, no clocking occurs inside the PowerPC 750CXe regardless of the SYSCLK input.
4. The SYSCLK limit is 133MHz, as specified in Table 4-6 on page 10. Contact IBM for SYSCLK frequencies above 133MHz.
5. With L1_TSTCLK tied to GND, processor to core frequency ratio is 9:1.
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