- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄67683 > IBM25PPC750CXEJP4022T 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256 PDF資料下載
參數(shù)資料
| 型號(hào)： | IBM25PPC750CXEJP4022T |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256 |
| 封裝： | 27 X 27 MM, PLASTIC, BGA-256 |
| 文件頁數(shù)： | 13/44頁 |
| 文件大?。?/td> | 416K |
| 代理商： | IBM25PPC750CXEJP4022T |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁當(dāng)前第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁
Data Sheet
PowerPC 750CXe RISC Microprocessor
Preliminary
Electrical and Thermal Characteristics
Page 12 of 36
750cxe_DD3.1_Dev_3_gen_mkt.fm.1.5
April 8, 2004
4.4 60x Bus Input AC Specifications
Table 4-7 provides the 60x bus input AC timing specifications for the PowerPC 750CXe as defined in
Figure 4-3 provides the input timing diagram for the PowerPC 750CXe.
Num
Characteristic
1.8V Mode
2.5V Mode
Unit
Notes
Min
Max
Min
Max
10a
Address/Data/Transfer attribute inputs valid to SYSCLK (input
setup)
1.10
—
1.25
—
ns
2
10b
All other inputs valid to SYSCLK (input setup)
1.10
—
1.25
—
ns
3
10c
Mode select input setup to HRESET (QACK)8
—
8
—
tsysclk
4, 5, 7
10d
TS to SYSCLK (input setup)
1.30
—
1.40
—
ns
—
10e
DBWO to SYSCLK (input setup)
1.50
—
1.60
—
ns
—
11a
SYSCLK to inputs invalid (input hold)
0.5
—
0.3
—
ns
2
11b
HRESET to mode select input hold (QACK)0
—
0
—
ns
4, 7
Notes:
1. Input specifications are measured from the midpoint voltage (+0.9V) of the signal in question to the midpoint voltage of the rising edge of the input
SYSCLK. Input and output timings are measured at the pin (see Figure 4-3).
2. Address/Data Transfer Attribute inputs are composed of all bidirectional and input signals except those listed in Note 3.
3. All other signal inputs are composed of the following: TA, QACK, and ARTRY.
4. The setup and hold time is with respect to the rising edge of HRESET (see Figure 4-4 on page 13).
5. t
SYSCLK, is the period of the external clock (SYSCLK) in nanoseconds (ns). The numbers given in the table must be multiplied by the period of
SYSCLK to compute the actual time duration (in ns) of the parameter in question.
6. These values are guaranteed by design and characterization, and are not tested.
7. This specification is for configuration mode select only. Also note that the HRESET must be held asserted for a minimum of 255 bus clocks after the
PLL relock time during the power-on reset sequence.
Figure 4-3. Input Timing Diagram
VM
SYSCLK
ALL INPUTS
VM = Midpoint Voltage (+0.8V for SYSCLK, +0.9V for all other I/O)
10b
10a
11a
VM
10d
10e
(Note: The 1.8 and 2.5V modes assume the same input midpoint for timing.)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM25PPC750CXEJP7022T | 32-BIT, 600 MHz, RISC PROCESSOR, PBGA256 |
| IBM25PPC750CXEJQ4022T | 32-BIT, 466 MHz, RISC PROCESSOR, PBGA256 |
| IBM25PPC750CXEJQ7022T | 32-BIT, 600 MHz, RISC PROCESSOR, PBGA256 |
| IBM25PPC750CXEJQ7023T | 32-BIT, 600 MHz, RISC PROCESSOR, PBGA256 |
| IBM25PPC750FX-DB0122T | 32-BIT, 600 MHz, RISC PROCESSOR, CBGA292 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM25PPC750CXEJP5512T | 制造商:IBM 功能描述: |
| IBM25PPC750CXEJP7012T | 制造商:IBM Microelectronics 功能描述:MPU 750XX RISC 32BIT 0.18UM 600MHZ 1.8V/2.5V 256BGA - Trays 制造商:IBM 功能描述:IBM IBM25PPC750CXEJP7012T Co-Processors |
| IBM25PPC750CXEJP7013T | 制造商:IBM 功能描述:IBMIBM25PPC750CXEJP7013T OEM EOL151207 |
| IBM25PPC750FL-GR0123V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
| IBM25PPC750FL-GR0124V | 制造商:IBM 功能描述:MPU 750XX RISC 32BIT - Trays |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。