參數(shù)資料
型號(hào)： IBM25PPC750CXEFP10-3T
元件分類： 微控制器/微處理器
英文描述： RISC PROCESSOR, PBGA256
封裝： 27 X 27 MM, PLASTIC, BGA-256
文件頁(yè)數(shù)： 24/42頁(yè)
文件大?。?/td> 492K
代理商： IBM25PPC750CXEFP10-3T
PowerPC 750CXe RISC Microprocessor Datasheet
Page 30
Version 1.0
February, 2001
Table 14: PowerPC 750CXe Microprocessor PLL Conguration
PLL_CFG
(0:3)
Processor to
Bus Frequency
Ratio
(r)
Frequency Range Supported by VCO having an example range of
VCO
MIN = 600 to VCOMAX = 1200MHz
5
SYSCLK
Core
bin
dec
Min
Max
Min
Max
0000
0
2.5x
Note 1
0001
1
7.5x
54
80
400
6005
0010
2
7x
57
86
0011
3
PLL Bypass2
N/A
0100
4
2x
Note 1
0101
5
6.5x
62
93
400
6005
0110
6
9x6, 10x
40
60
400
6005
0111
7
4.5x
89
133
400
6005
1000
8
3x
133
1334
1001
9
5.5x
73
109
1010
10
4x
100
150
1011
11
5x
80
120
1100
12
8x
50
75
1101
13
6x
67
100
1110
14
3.5x
114
172
1111
15
Off3
N/A
Off
Note:
1. The 2X and 2.5XProcessor to Bus Ratios are currently not supported.
2. In PLL-bypass mode, the SYSCLK input signal clocks the internal processor directly, the PLL is disabled, and the bus mode is set for
1:1 mode operation. This mode is intended for factory use only. Note: The AC timing specifications given in the document do not apply
in PLL-bypass mode.
3. In Clock - off mode, no clocking occurs inside the PowerPC 750CXe regardless of the SYSCLK input.
4. The SYSCLK limit is 133MHz, as specified in Table 6 on page 15. Contact IBM for SYSCLK frequencies above 133MHz.
5. VCO
MAX is specified in this table by the maximum core processor speed. The VCO maximum of 1200MHz reflects a processor core
speed of 600MHz, which is not currently supported.
6. With L1_TSTCLK tied to GND, processor to core frequency ratio is 9:1.
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