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參數(shù)資料
| 型號： | IBM25PPC750-DB0M2500 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 250 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 10/42頁 |
| 文件大小： | 496K |
| 代理商： | IBM25PPC750-DB0M2500 |
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Page 18
v 3.2
Datasheet
7/15/99
PowerPC 750TM SCM RISC Microprocessor
Preliminary Copy
L2 Bus Output AC Specications
Table 12 provides the L2 bus output interface AC timing specifications for the 750 as defined in Figure 15.
Table 12. L2 Bus Output Interface AC Timing Specications1
See Table 2 for operating conditions, L2OVDD = 3.3 ± 5% VDC or VDD
7, C
L = 20pF
3
Num
Characteristic
L2CR[14-15] is equivalent to:
Unit
Notes
002
01
10
11
Min
Max
Min
Max
Min
Max
Min
Max
26
L2SYNC_IN to output valid
for processors 266MHz and
below
—
5.0
—
5.5
—
Rsv5
—
Rsv5
ns
26
L2SYNC_IN to output valid
for processor at 275MHz
—
4.5
—
5.0
—
Rsv5
—
Rsv5
ns
26
L2SYNC_IN to output valid
for processor at 300MHz
—
4.0
—
4.5
—
Rsv5
—
Rsv5
ns
27
L2SYNC_IN to output hold
0.5
—
1.0
—
Rsv5
—
Rsv5
—ns
4
28
L2SYNC_IN to high imped-
ance
—
4.0
—
4.5
—
Rsv5
—
Rsv5
ns
6
Note:
1. All outputs are measured from the midpoint voltage of the rising edge of L2SYNC_IN to the midpoint voltage (1.4V) of
the signal in question. The output timings are measured at the pins.
2.The outputs are valid for both single-ended and differential L2CLK modes. For ow-thru and pipelined reg-reg synchro-
nous burst SRAMs, L2CR[14-15] = 00 is recommended. For pipelined late-write synchronous burst SRAMs, L2CR[14-
15] = 01 is recommended.
3. All maximum timing specications assume CL = 20pF.
4. This measurement assumes CL= 5pF.
5. Reserved for future use.
6. Guaranteed by design and characterization, and not tested.
7. For SRAMs that can be operated at the VDDvoltage, L2OVDD can also be tied to the VDD voltage.
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