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參數(shù)資料
| 型號： | IBM25EMPPC750LDBE3000 |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 32-BIT, 300 MHz, RISC PROCESSOR, CBGA360 |
| 封裝： | 25 X 25 MM, 1.27 MM PITCH, CERAMIC, BGA-360 |
| 文件頁數(shù)： | 13/50頁 |
| 文件大小： | 600K |
| 代理商： | IBM25EMPPC750LDBE3000 |
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Page 16
Version 1.51
PowerPC 740 and PowerPC 750 Datasheet
5/20/99
PowerPC 740 and PowerPC 750 Embedded Microprocessor
IBM CMOS 0.20 um Copper Technology EMPPC740L and EMPPC750L
L2 Clock AC Specications
The following table provides the L2CLK output AC timing specifications for the 750 as defined in Figure 6.
L2CLK Output AC Timing Specications
See Table “Recommended Operating Conditions,” on page 7, for operating conditions.
Num
Characteristic
Min
Max
Unit
Notes
L2CLK frequency
80
233
MHz
1, 4
22
L2CLK cycle time
4.3
12.5
ns
23
L2CLK duty cycle
50
%
2
Internal DLL-relock time
640
—
L2CLK
3
Note:
1. L2CLK outputs are L2CLKOUTA, L2CLKOUTB and L2SYNC_OUT pins. The internal design supports higher L2CLK frequencies; however, the L2 I/O
drivers have been designed to support a 150MHz L2 bus loaded with 4 off-the-shelf pipelined synchronous burst SRAMs. Running the L2 bus beyond
150 MHz would require tightly coupled customized SRAMs or a multi-chip module (MCM) implementation. The L2CLK frequency to core frequency set-
tings must be chosen such that the resulting L2CLK frequency and core frequency do not exceed their respective maximum or minimum operating fre-
quencies. L2CLKOUTA and L2CLKOUTB must have equal loading.
2. The nominal duty cycle of the L2CLK is 50% measured at midpoint voltage.
3. The DLL re-lock time is specified in terms of L2CLKs. The number in the table must be multiplied by the period of L2CLK to compute the actual time
duration in nanoseconds. Re-lock timing is guaranteed by design and characterization, and is not tested.
4. The L2CR [L2SL] bit should be set for L2CLK frequencies less than 110MHz.
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