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參數(shù)資料
| 型號： | IBM13T8644HPB |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Modules）(8M x 64 144腳小外形雙列直插同步動態(tài)RAM模塊) |
| 中文描述： | 8米× 64 SDRAM的內(nèi)存蘇（小外形雙列直插式內(nèi)存模塊）（8米× 64 144腳小外形雙列直插同步動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 9/17頁 |
| 文件大小： | 325K |
| 代理商： | IBM13T8644HPB |
IBM13T8644HPB
IBM13T8644HPC
8M x 64 SDRAM SO DIMM
01L5951.E24562B
5/99
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 9 of 17
Operating, Standby and Refresh Currents
(T
A
=
0 to
+
70
°
C, V
DD
=
3.3V
±
0.3V)
Parameter
Symbol
Test Condition
Units
Notes
Operating Current
t
RC
=
t
RC
(min), t
CK
=
min
Active-Precharge command cycling
without Burst operation
I
DD1
1 bank operation
440
mA
1, 2
Precharge Standby Current in Power
Down Mode
I
DD2P
CKE
≤
V
IL
(max), t
CK
=
min, S0, S1
=
V
IH
(min)
8
mA
I
DD2Ps
CKE
≤
V
IL
(max), t
CK
=
Infinity, S0, S1
=
V
IH
(min)
8
mA
Precharge Standby Current in Non-
Power Down Mode
I
DD2N
CKE
≥
V
IH
(min), t
CK
=
min, S0, S1
=
V
IH
(
min)
200
mA
3
I
DD2NS
CKE
≥
V
IH
(min), t
CK
=
Infinity, S0, S1
=
V
IH (
min)
40
mA
4
No Operating Current
(Active state: 4 bank)
I
DD3N
CKE
≥
V
IH
(min), t
CK
=
min, S0, S1
=
V
IH (
min)
240
mA
3
I
DD3P
CKE
≤
V
IL
(max), t
CK
=
min, S0, S1
=
V
IH (
min) (Power
Down Mode)
56
mA
5
Burst Operating Current
I
DD4
t
CK
=
min, Read/ Write command cycling
720
mA
2, 6
Auto (CBR) Refresh Current
I
DD5
t
CK
=
min, CBR command cycling
880
mA
Self Refresh Current
I
DD6
CKE0
≤
0.2V
3.2
mA
Serial PD Device Standby Current
I
SB5
V
IN
=
GND or V
DD
30
μ
A
7
Serial PD Device Active Power Supply
Current
I
CCA
SCL Clock Frequency
=
100KHz
1
mA
8
1. These parameters depend on the cycle rate and are measured with the cycle determined by the minimum value of t
CK
and t
RC
.
Input signals are changed up to three times during t
RC
(min).
2. The specified values are obtained with the output open.
3. Input signals are changed once during three clock cycles.
4. Input signals are stable.
5. Active Standby current will be higher if Clock Suspend is entered during a Burst Read cycle (add 1mA per DQ).
6. Input signals are changed once during t
CK
(min).
7. V
DD
=
3.3V.
8. Input pulse levels V
DD
x 0.1 to V
DD
x 0.9, input rise and fall times 10ns, input and output timing levels V
DD
x 0.5, output load 1 TTL
gate and CL
=
100pf.
Discontinued (8/99 - last order; 12/99 - last ship)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM13T8644HPC | 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Modules）(8M x 64 144腳小外形雙列直插同步動態(tài)RAM模塊) |
| IBM13T8644HPD | One Bank 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(1組 8M x 64 PC100小外形雙列直插同步動態(tài)RAM模塊) |
| IBM13T8644HPE | One Bank 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(1組 8M x 64 PC100小外形雙列直插式同步動態(tài)RAM模塊) |
| IBM13T8644MPD | Two Bank 8M x 64 SDRAM SO DIMM（Small Outline Dual In-line Memory Module）(2組 8M x 64 PC100小外形雙列直插同步動態(tài)RAM模塊) |
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