參數(shù)資料
型號(hào)： IBM11N8845HB
廠商： IBM Microeletronics
英文描述： 8M x 72 Chip-Kill Protect ECC-on-DIMM Module(8M x 72 帶糾錯(cuò)代碼保護(hù)的小外形雙列直插動(dòng)態(tài)RAM模塊)
中文描述： 8米× 72片，殺死保護(hù)ECC的上內(nèi)存模塊（8米× 72帶糾錯(cuò)代碼保護(hù)的小外形雙列直插動(dòng)態(tài)內(nèi)存模塊）
文件頁(yè)數(shù)： 11/29頁(yè)
文件大?。?/td> 497K
代理商： IBM11N8845HB
IBM11N8845HB
Preliminary
8M x 72 Chip-Kill Protect ECC-on-DIMM Module
75H5486
GA14-4641-00
Revised 11/96
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 11 of 29
Refresh Cycle
Symbol
Parameter
-6R
Unit
Notes
Min
Max
t
CHR
CAS Hold Time
(CAS before RAS Refresh Cycle)
10
—
ns
t
CSR
CAS Setup Time
(CAS before RAS Refresh Cycle)
5
—
ns
t
WRP
WE Setup Time
(CAS before RAS Refresh Cycle)
10
—
ns
t
WRH
WE Hold Time
(CAS before RAS Refresh Cycle)
10
—
ns
t
RPC
RAS Precharge to CAS Hold Time
5
—
ns
t
REF
Refresh Period
—
64
ms
1
1. 4096 refreshes are required every 64ms (12/11 addressing).
Presence Detect Read and Write Cycle
Symbol
Parameter
Min
Max
Unit
Notes
f
SCL
SCL Clock Frequency
100
kHZ
T
I
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
t
AA
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
t
BUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
t
HD:STA
Start Condition Hold Time
4.0
t
LOW
Clock Low Period
4.7
t
HIGH
Clock High Period
4.0
t
SU:STA
Start Condition Setup Time(for a Repeated Start Condition)
4.7
t
HD:DAT
Data in Hold Time
0
t
SU:DAT
Data in Setup Time
250
ns
t
r
SDA and SCL Rise Time
1
μ
s
t
f
SDA and SCL Fall Time
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
μ
s
t
DH
Data Out Hold Time
300
ns
t
WR
Write Cycle Time
15
ms
1
1. The write cycle time(tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program
cycle. During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resis-
tor, and the device does not respond to its slave address.
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