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參數(shù)資料
| 型號： | IBM11N8735H |
| 廠商： | IBM Microeletronics |
| 英文描述： | 8M x 72 DRAM Module(8M x 72 動態(tài)RAM模塊) |
| 中文描述： | 8米× 72內存（8米× 72動態(tài)內存模塊） |
| 文件頁數(shù)： | 13/31頁 |
| 文件大?。?/td> | 564K |
| 代理商： | IBM11N8735H |
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IBM11N8645H
IBM11N8735H
8M x 64/72 DRAM Module
54H8530.E24352A
Revised 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 13 of 31
Refresh Cycle
Symbol
Parameter
-50
-60
Unit
Notes
Min
Max
Min
Max
t
CHR
CAS Hold Time
(CAS before RAS Refresh Cycle)
10
—
10
—
ns
t
CSR
CAS Setup Time
(CAS before RAS Refresh Cycle)
5
—
5
—
ns
t
WRP
WE Setup Time
(CAS before RAS Refresh Cycle)
10
—
10
—
ns
t
WRH
WE Hold Time
(CAS before RAS Refresh Cycle)
10
—
10
—
ns
t
RPC
RAS Precharge to CAS Hold Time
5
—
5
—
ns
t
REF
Refresh Period
—
64
—
64
ms
1
1. 4096 refreshes are required every 64ms.
Presence Detect Read and Write Cycle
Symbol
Parameter
Min
Max
Unit
Notes
f
SCL
SCL Clock Frequency
100
kHZ
T
I
Noise Suppression Time Constant at SCL, SDA Inputs
100
ns
t
AA
SCL Low to SDA Data Out Valid
0.3
3.5
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
μ
s
t
BUF
Time the Bus Must Be Free before a New Transmission Can Start
4.7
t
HD:STA
Start Condition Hold Time
4.0
t
LOW
Clock Low Period
4.7
t
HIGH
Clock High Period
4.0
t
SU:STA
Start Condition Setup Time(for a Repeated Start Condition)
4.7
t
HD:DAT
Data in Hold Time
0
t
SU:DAT
Data in Setup Time
250
ns
t
r
SDA and SCL Rise Time
1
μ
s
t
f
SDA and SCL Fall Time
300
ns
t
SU:STO
Stop Condition Setup Time
4.7
μ
s
t
DH
Data Out Hold Time
300
ns
t
WR
Write Cycle Time
15
ms
1
1. The write cycle time(tWR) is the time from a valid stop condition of a write sequence to the end of the internal erase/program cycle.
During the write cycle, the bus interface circuits are disabled, SDA is allowed to remain high per the bus-level pull-up resistor, and
the device does not respond to its slave address.
Discontinued (9/98 - last order; 3/99 last ship)
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