- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄379204 > IBM11M4730CH (IBM Microeletronics) 4M x 72 DRAM Module(4M x 72 動態(tài)RAM模塊) PDF資料下載
參數(shù)資料
| 型號： | IBM11M4730CH |
| 廠商： | IBM Microeletronics |
| 英文描述： | 4M x 72 DRAM Module(4M x 72 動態(tài)RAM模塊) |
| 中文描述： | 4米× 72內(nèi)存（4米× 72動態(tài)內(nèi)存模塊） |
| 文件頁數(shù)： | 7/27頁 |
| 文件大?。?/td> | 500K |
| 代理商： | IBM11M4730CH |
第1頁第2頁第3頁第4頁第5頁第6頁當(dāng)前第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁
IBM11M4730CH IBM11M4730CB
IBM11M4730CF
4M x 72 DRAM Module
64G1557.E20999D
Revised 4/98
IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
Page 7 of 27
.
Read, Write, Read-Modify-Write, and Refresh Cycles
(Common Parameters)
Symbol
Parameter
-60
Unit
Notes
Min
Max
t
RC
Random Read or Write Cycle Time
110
—
ns
t
RP
RAS Precharge Time
40
—
ns
t
CP
CAS Precharge Time
10
—
ns
t
RAS
RAS Pulse Width
60
10K
ns
t
CAS
CAS Pulse Width
15
10K
ns
1
t
ASR
Row Address Setup Time
5
—
ns
t
RAH
Row Address Hold Time
8
—
ns
t
ASC
Column Address Setup Time
2
—
ns
t
CAH
Column Address Hold Time
10
—
ns
t
RCD
RAS to CAS Delay Time
18
40
ns
2
t
RAD
RAS to Column Address Delay Time
13
25
ns
3
t
RSH
RAS Hold Time
20
—
ns
t
CSH
CAS Hold Time
58
—
ns
t
CRP
CAS to RAS Precharge Time
10
—
ns
t
ODD
OE to D
IN
Delay Time
20
—
ns
4
t
DZO
OE Delay Time from D
IN
-2
—
ns
5
t
DZC
CAS Delay Time from D
IN
-2
—
ns
5
t
AR
Column Address Hold Time Referenced to RAS
—
—
—
6
t
T
Transition Time (Rise and Fall)
3
30
ns
1. The minimum t
CAS
requires t
CSH
to be met for both writes and reads. Also, because of the buffer, the minimum t
CAS
for a read
cycle must be extended to guarantee the data out window (t
OH
) in the application. For example, a t
CAS
of 15ns plus a minimum t
OH
of 2ns would result in turning data out of the DIMM at 17ns (3ns before max t
CAC
of 20ns).
2. Operation within the t
RCD
(max) limit ensures that t
RAC
(max) can be met. The t
RCD
(max) is specified as a reference point only: If
t
RCD
is greater than the specified t
RCD
(max) limit, then access time is controlled by t
CAC.
3. Operation within the t
RAD
(max) limit ensures that t
RAC
(max) can be met. The t
RAD
(max) is specified as a reference point only: If
t
RAD
is greater than the specified t
RAD
(max) limit, then access time is controlled by t
AA.
4. Either t
CDD
or t
ODD
must be satisfied.
5. Either t
DZC
or t
DZO
must be satisfied.
6. This timing parameter is not applicable to this product, but applies to a related product in this family.
Discontinued (9/98 - last order; 3/99 last ship)
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| IBM11M4730HB | 4M x 72 DRAM Module(4M x 72 動態(tài)RAM模塊) |
| IBM11M4730H | 4M x 72 DRAM Module(4M x 72 動態(tài)RAM模塊) |
| IBM11M4735HB | 4M x 72 DRAM Module(4M x 72 動態(tài)RAM模塊) |
| IBM11M8730C | 8M x 72 DRAM Module(8M x 72 動態(tài)RAM模塊) |
| IBM11M8730CB | 8M x 72 DRAM Module(8M x 72 動態(tài)RAM模塊) |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| IBM14H5481 | 制造商:AVED Memory Products 功能描述: |
| IBM14H5540 | 制造商:AVED MEMORY PRODUCTS 功能描述: 制造商:AVED Memory Products 功能描述: |
| IBM17R8251 | 制造商:AVED Memory Products 功能描述: |
| IBM17R8252 | 制造商:AVED Memory Products 功能描述: |
| IBM1805T | 制造商:Schneider Electric 功能描述:IBM1805T |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。