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參數(shù)資料
| 型號： | IA8344 |
| 廠商： | Innovasic Semiconductor |
| 英文描述： | SDLC COMMUNICATIONS CONTROLLER |
| 中文描述： | SDLC的通信控制器 |
| 文件頁數(shù)： | 27/49頁 |
| 文件大?。?/td> | 220K |
| 代理商： | IA8344 |
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IA8044/IA8344
Data Sheet
SDLC COMMUNICATIONS CONTROLLER
SIU – Serial Interface Unit
The SIU is a serial interface customized to support SDLC/HDLC protocol. As such it supports
Zero Bit insertion/deletion, flags automatic access recognition and a 16 bit CRC. The SIU has two
modes of operation AUTO and FLEXIBLE. The AUTO mode uses a subset of the SDLC
protocol implemented in hardware. This frees the CPU from having to respond to every frame but
limits the frame types. In the FLEXIBLE mode every frame is under CPU control and therefore
more options are available. The SIU is controlled by and communicates to the CPU by using
several special function registers (SFRs). Data transmitted by or received by the SIU is stored in the
192 byte internal RAM in blocks referred to as the transmit and receive buffers. The SIU can
support operation in one of three serial data link configurations: 1) half-duplex, point-to-point, 2)
half-duplex, multipoint, 3) loop mode.
SIU Special Function Registers
The CPU controls the SIU and receives status from the SIU via eleven special function registers.
The Serial Interface Unit Control Registers are detailed below:
Serial Mode Register (SMD):
The serial mode register sets the operational mode of the SIU. The CPU can read and write SMD.
The SIU can read SMD. To prevent conflicts between CPU and SIU accesses to SMD the CPU
should write SMD only when RTS and RBE bits in the STS register are both zero. SMD is normally
only accessed during initialization. This register is byte addressable.
SMD
Bit: 7
6
5
4
SCM2
SCM1
SCM0
NRZI
SMD.0
NFCS
When set selects No FCS field contained in the SDLC frame.
SMD.1
NB
Non-buffered mode. No control field contained in SDLC frame.
SMD.2
PFS
Pre-frame sync mode. When set causes two bytes to be
transmitted before the first flag of the frame for DPLL
synchronization. If NRZI is set 00H is transmitted otherwise 55H.
This ensures that 16 transitions are sent before the opening flag.
SMD.3
LOOP
When set selects loop configuration else point-to-point mode.
SMD.4
NRZI
When set selects NRZI encoding otherwise NRZ.
SMD.5
SCM0
Select clock mode - bit 0.
SMD.6
SCM1
Select clock mode - bit 1.
SMD.7
SCM2
Select clock mode - bit 2.
Copyright
2003
innov
ASIC
The End of Obsolescence
ENG210010112-00
www.innovasic.com
Customer Support:
Page 27 of 49
1-888-824-4184
3
2
1
0
LOOP
PFS
NB
NFCS
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| IA8344-PDW40I-01 | SDLC COMMUNICATIONS CONTROLLER |
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| IA8X44 | SDLC COMMUNICATIONS CONTROLLER |
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| IA8344-PDW40I-00 | 制造商:INNOVASIC 制造商全稱:INNOVASIC 功能描述:SDLC COMMUNICATIONS CONTROLLER |
| IA8344-PDW40I-01 | 制造商:INNOVASIC 制造商全稱:INNOVASIC 功能描述:SDLC COMMUNICATIONS CONTROLLER |
| IA8344-PLC44I-00 | 制造商:INNOVASIC 制造商全稱:INNOVASIC 功能描述:SDLC COMMUNICATIONS CONTROLLER |
| IA8344-PLC44I-01 | 制造商:INNOVASIC 制造商全稱:INNOVASIC 功能描述:SDLC COMMUNICATIONS CONTROLLER |
| IA85 | 制造商:CELDUC 制造商全稱:celduc-relais 功能描述:REED SWITCH NORMALY OPEN, DRY CONTACT |
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