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參數(shù)資料
| 型號： | IA8344-PLC44I-01 |
| 廠商： | Innovasic Semiconductor |
| 英文描述： | SDLC COMMUNICATIONS CONTROLLER |
| 中文描述： | SDLC的通信控制器 |
| 文件頁數(shù)： | 28/49頁 |
| 文件大?。?/td> | 220K |
| 代理商： | IA8344-PLC44I-01 |
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IA8044/IA8344
Data Sheet
SDLC COMMUNICATIONS CONTROLLER
SMD Select Clock Mode Bits
Copyright
2003
innov
ASIC
The End of Obsolescence
ENG210010112-00
www.innovasic.com
Customer Support:
Page 28 of 49
1-888-824-4184
SCM
2 1 0
0 0 0
0 0 1
0 1 0
0 1 1
1 0 0
1 0 1
1 1 0
1 1 1
Status/Command Register (STS):
The Status/Command register provides SIU control from and status to the CPU. The SIU can read
the STS and can write certain bits in the STS. The CPU can read and write the STS. Accessing the
STS by the CPU via 2 cycle instructions (JBC bit,rel and MOV bit,C) should not be used. STS is bit
addressable.
STS
Bit: 7
6
5
4
TBF
RBE
RTS
SI
STS.0
RBP
Receive buffer protect. When set prevents writing of data into
the receive buffer. Causes RNR response instead of RR in AUTO
mode.
STS.1
AM
Auto mode. Dual purpose bit depending upon the setting of bit NB
(SMD.1). If NB is cleared, AM selects the AUTO mode when
set, Flexible mode when clear. If NB is set, AM selects the addressed
mode when set and the non-addressed mode when clear. The SIU
can clear AM.
STS.2
OPB
Optional poll bit. When set the SIU will AUTO respond to an
optional poll (UP with P=0). The SIU can set or clear the OPB.
STS.3
BOV
Receive buffer overrun. The SIU can set or clear BOV.
STS.4
SI
SIU interrupt. This bit is set by the SIU and should be cleared
by the CPU before returning from the interrupt routine.
STS.5
RTS
Request to send. This bit is set when the SIU is ready to
transmit or is transmitting. May be written by the SIU in AUTO
mode. RTS is only applied to the external pin in non-loop mode.
Can be thought of as a Transmit Enable. Note: RTS signal at the
pin (P1.6) is the inverted version of this bit.
Clock Mode
Data Rate
(Bits/sec)*
0 – 2.4M**
244 – 62.5K
0 – 375K
0 – 187.5K
375K
187.5K
Externally clocked
Undefined
Self clocked, timer overflow
Undefined
Self clocked, external 16X
Self clocked, external 32X
Self clocked, internal fixed
Self clocked, internal fixed
* based on a12 MHz crystal frequency
** 0 – 1M bps in loop configuration
3
2
1
AM
0
BOV
OPB
RBP
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