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參數(shù)資料
| 型號： | IA80C152JD |
| 廠商： | Innovasic Semiconductor |
| 英文描述： | UNIVERSAL COMMUNICATIONS CONTROLLER |
| 中文描述： | 通用通信控制器 |
| 文件頁數(shù)： | 1/32頁 |
| 文件大?。?/td> | 232K |
| 代理商： | IA80C152JD |
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I
A80C152
UNIVERSAL COMMUNICATIONS CONTROLLER
FEATURES
Form, Fit, and Function Compatible
with the Intel
a
80C152
Packaging options available
48 Pin Plastic or Ceramic DIP
68 Pin Plastic or Ceramic LCC
8051 Core with:
Direct Memory Access(DMA)
Global Serial Channel (GSC)
MCS
a
- 51 Compatible UART
Two Timers/Counters
Maskable Interrupts
Memory
256 Bytes Internal RAM
64K Bytes Program Memory
64K Bytes Data Memory
5 or 7 I/O Ports
Up to 16.5 MHz Clock Frequency
Preliminary Data Sheet
Copyright
2000
innov
ASIC
[_________
The End of Obsolescence
Two-Channel DMA With Multiple
Transfer Modes
GSC Provides Support for Multiple
Protocols
CSMA/CD
SDLC/HDLC
User Definable
Separate Transmit & Receive FIFOs
Special Protocol Features
Up to 2.0625 Mbps Serial
Operation
CSMA and SDLC Frame Formats
with CRC Checking
Manchester, NRZ, & NRZI Data
Encoding
Collision Detection & Resolution
in CSMA Mode
Selectable Full/Half Duplex
Figure 1 - 48 Pin DIP Pinout
(6)
(HLDn) P1.5
(1)
(GRXD) P1.0
(2)
(GTXD) P1.1
(3)
(DENn) P1.2
(4)
(TXCn) P1.3
(5)
(RXCn) P1.4
(7)
(HLDAn) P1.6
(8)
P1.7
(9)
RESETn
(10)
(RXD) P3.0
(11)
(TXD) P3.1
(12)
(INT0n) P3.2
(13)
(INT1n) P3.3
(14)
(T0) P3.4
48 Pin DIP
JA/JC
IA80152
(48)
VDD
(47)
(46)
(45)
(44)
(43)
(42)
(41)
(40)
P4.7
(39)
EA
(38)
ALE
(37)
PSENn
(36)
P2.7 (A15)
(35)
P2.6 (A14)
(20)
(A / D2) P0.2
(15)
(T1) P3.5
(16)
(WRn) P3.6
(17)
(RDn) P3.7
(18)
(A / D0) P0.0
(19)
(A / D1) P0.1
(21)
(A / D3) P0.3
(22)
XTAL2
(23)
XTAL1
(24)
Vss
(34)
(33)
(32)
(31)
(30)
(29)
(28)
(27)
(26)
(25)
P2.5 (A13)
P2.4 (A12)
P2.3 (A11)
P2.2 (A10)
P2.1 (A9)
P2.0 (A8)
P0.7 (A / D7)
P0.6 (A / D6)
P0.5 (A / D5)
P0.4 (A / D4)
P4.6
P4.5
P4.4
P4.3
P4.2
P4.1
P4.0
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