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| 型號(hào)： | I843034AY-06 |
| 廠商： | INTEGRATED DEVICE TECHNOLOGY INC |
| 元件分類(lèi)： | 時(shí)鐘產(chǎn)生/分配 |
| 英文描述： | 750 MHz, PROC SPECIFIC CLOCK GENERATOR, PQFP48 |
| 封裝： | 7 X 7 MM, 1.40 MM HEIGHT, MS-026, LQFP-48 |
| 文件頁(yè)數(shù)： | 12/21頁(yè) |
| 文件大?。?/td> | 976K |
| 代理商： | I843034AY-06 |
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IDT / ICS 3.3V LVPECL FREQUENCY SYNTHESIZER
2
ICS843034AY-06 REV. A MARCH 7, 2007
ICS843034-06
FEMTOCLOCKS MULTI-RATE 3.3V LVPECL FREQUENCY SYNTHESIZER
PRELIMINARY
automatically occur during power-up. The TEST output is LOW
when operating in the parallel input mode. The relationship
between the VCO frequency, the crystal frequency and the M
divider is defined as follows:
The M value and the required values of M0 through M8 are shown
in Table 4B to program the VCO Frequency Function Table. Valid
M values for which the PLL will achieve lock for a 25MHz refer-
ence are defined as 23
≤ M ≤ 30. The frequency out is defined as
follows:
Serial operation occurs when nP_LOAD is HIGH and S_LOAD
is LOW. The shift register is loaded by sampling the S_DATA
bits with the rising edge of S_CLOCK. The contents of the shift
register are loaded into the M divider and NA output divider
when S_LOAD transitions from LOW-to-HIGH. The M divide
and NA output divide values are latched on the HIGH-to-LOW
transition of S_LOAD. If S_LOAD is held HIGH, data at the
S_DATA input is passed directly to the M divider and NA output
divider on each rising edge of S_CLOCK. The serial mode can
be used to program the M and NA bits and test bits T1 and T0.
The internal registers T0 and T1 determine the state of the
TEST output as follows:
FUNCTIONAL DESCRIPTION
NOTE: The functional description that follows describes opera-
tion using a 25MHz crystal. Valid PLL loop divider values for
different crystal or input frequencies are defined in the Input
Frequency Characteristics, Table 5, NOTE 1.
The ICS843034-06 features a fully integrated PLL and there-
fore requires no external components for setting the loop band-
width. A fundamental crystal is used as the input to the on-
chip oscillator. The output of the oscillator is fed into the phase
detector. A 25MHz crystal provides a 25MHz phase detector
reference frequency. The VCO of the PLL operates over a range
of 560MHz to 750MHz. The output of the M divider is also
applied to the phase detector.
The phase detector and the M divider force the VCO output
frequency to be M times the reference frequency by adjusting the
VCO control voltage. Note that for some values of M (either too
high or too low), the PLL will not achieve lock. The output of the
VCO is scaled by a divider prior to being sent to each of the
LVPECL output buffers. The divider provides a 50% output duty
cycle.
The ICS843034-06 supports either serial or parallel programming
modes to program the M feedback divider and N output divider.
Figure 1 shows the timing diagram for each mode. In parallel
mode, the nP_LOAD input is initially LOW. The data on the M and
NA inputs are passed directly to the M divider and N output divid-
ers. On the LOW-to-HIGH transition of the nP_LOAD input, the
data is latched and the M and N dividers remain loaded until the
next LOW transition on nP_LOAD or until a serial event occurs.
As a result, the M and NA bits can be hardwired to set the M
divider and NA output divider to a specific default state that will
T1
T0
TEST Output
00
LOW
0
1
S_Data, Shift Register Output
1
0
Output of M divider
1
FOUTA0 same frequency
fVCO = fxtal x M
FOUT = fVCO = fxtal x M
N
FIGURE 1. PARALLEL & SERIAL LOAD OPERATIONS
SERIAL LOADING
PARALLEL LOADING
M, N
t
S
t
S
t
H
t
S
t
H
Time
SSC3 SSC2 SSC1 SSC0
T1
T0
NU
NA2
NA1
NA0
M8
M7
M6
M5
M4
M3
M2
M1
M 0
S_CLOCK
S_DATA
S_LOAD
nP_LOAD
M0:M8, NA0:NA2
nP_LOAD
S_LOAD
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