參數(shù)資料
型號: I74F50729D-T
廠商: NXP SEMICONDUCTORS
元件分類: 鎖存器
英文描述: F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDSO14
封裝: PLASTIC, SO-14
文件頁數(shù): 11/12頁
文件大?。?/td> 104K
代理商: I74F50729D-T
Philips Semiconductors
Product data
74F50729
Synchronizing dual D-type flip-flop with edge-triggered
set and reset and metastable immune characteristics
2003 Jan 20
8
AC SETUP REQUIREMENTS
SYMBOL
PARAMETER
TEST
CONDITION
LIMITS
CONDITION
Tamb = +25 °C
Tamb = 0 °C to +70 °C
Tamb = –40 °C to +85 °C
VCC = +5.0 V
VCC = +5.0 V ± 10%
UNIT
CL = 50 pF,
RL = 500
CL = 50 pF,
RL = 500
CL = 50 pF,
RL = 500
MIN
TYP
MAX
MIN
MAX
MIN
MAX
tsu (H)
tsu(L)
Setup time, high or low
Dn to CPn
Waveform 1
1.5
2.0
ns
th (H)
th (L)
Hold time, high or low
Dn to CPn
Waveform 1
1.0
1.5
ns
tw (H)
tw (L)
CPn pulse width,
high or low
Waveform 2
3.0
4.0
3.5
6.0
3.5
6.0
ns
tw (L)
SDn, RDn pulse width, low
Waveform 3
3.5
4.0
ns
trec
Recovery time
SDn, RDn to CPn
Waveform 3
6.0
6.5
ns
trec
Recovery time
SDn to RDn or RDn to SDn
Waveform 3
1.0
ns
AC WAVEFORMS
For all waveforms, VM = 1.5 V.
The shaded areas indicate when the input is permitted to change for predictable output performance.
VM
CPn
VM
tsu(H)
th(H)
Dn
Qn
VM
tw(H)
1/fmax
tsu(L)
th(L)
VM
tPLH
Qn
tw(L)
tPHL
tPLH
SF00049
Waveform 1. Propagation delay for data to output,
data set-up time and hold times,
and clock width, and maximum clock frequency
SDn or RDn
VM
trec
CPn
SF00603
Waveform 3. Recovery time for set or reset to output
VM
RDn
VM
Qn
VM
tPLH
Qn
tw(L)
tPHL
tPLH
SDn
VM
tw(L)
SF00050
Waveform 2. Propagation delay for set and reset to output,
set and reset pulse width
Qn, Qn
VM
tsk(o)
Qn, Qn
SF00590
Waveform 4. Output skew
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相關代理商/技術(shù)參數(shù)
參數(shù)描述
I74F50729N 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics
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