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參數(shù)資料
| 型號： | I74F50728N |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 通用總線功能 |
| 英文描述： | Synchronizing cascaded dual positive edge-triggered D-type flip-flop |
| 中文描述： | F/FAST SERIES, DUAL POSITIVE EDGE TRIGGERED D FLIP-FLOP, COMPLEMENTARY OUTPUT, PDIP14 |
| 封裝： | 0.300 INCH, PLASTIC, DIP-14 |
| 文件頁數(shù)： | 3/12頁 |
| 文件大?。?/td> | 89K |
| 代理商： | I74F50728N |
Philips Semiconductors
Product specification
74F50728
Synchronizing cascaded dual positive
edge-triggered D-type flip-flop
September 14, 1990
3
PIN CONFIGURATION
14
13
12
11
10
9
8
7
6
5
4
3
2
1
GND
V
CC
SD1
Q1
Q1
CP1
RD1
D1
RD0
D0
Q0
CP0
SD0
Q0
SF00605
LOGIC SYMBOL
D1
D0
Q0 Q0 Q1 Q1
5
6
9
8
2
12
V
= Pin 14
GND = Pin 7
CP0
SD0
RD0
CP1
SD1
RD1
3
4
1
11
10
13
SF00606
IEC/IEEE SYMBOL
3
6
9
8
&
S
C1
1D
R
S
C2
2D
R
SF00607
4
3
2
1
10
11
12
13
LOGIC DIAGRAM
D
Q
Q
CP
D
Q
Q
CP
Qn
Q n
CPn
5, 9
6, 8
4, 10
2, 12
3, 11
1, 13
V
= Pin 14
GND = Pin 7
SDn
SF00608
Dn
RDn
NOTE:
Data entering the flip–flop requires two clock cycles to
arrive at the output
.
SYNCHRONIZING SOLUTIONS
Synchronizing incoming signals to a system clock has proven to be
costly, either in terms of time delays or hardware. The reason for this
is that in order to synchronize the signals a flip–flop must be used to
”capture” the incoming signal. While this is perhaps the only way to
synchronize a signal, to this point, there have been problems with
this method. Whenever the flop’s setup or hold times are violated
the flop can enter a metastable state causing the outputs in turn to
glitch, oscillate, enter an intermediate state or change state in some
abnormal fashion. Any of these conditions could be responsible for
causing a system crash. To minimize this risk, flip–flops are often
cascaded so that the input signal is captured on the first clock pulse
and released on the second clock pulse (see Fig.1). This gives the
first flop about one clock period minus the flop delay and minus the
second flop’s clock–to–Q setup time to resolve any metastable
condition. This method greatly reduces the probability of the outputs
of the synchronizing device displaying an abnormal state but the
trade-off is that one clock cycle is lost to synchronize the incoming
data and two separate flip–flops are required to produce the
cascaded flop circuit. In order to assist the designer of synchronizing
circuits Philips Semiconductors is offering the 74F50728.
D
Q
Q
CP
D
Q
Q
CP
Q OUTPUT
Q OUTPUT
DATA
CLOCK
SF00609
Figure 1.
The 50728 consists of two pair of cascaded D–type flip–flops with
metastable immune features and is pin compatible with the 74F74.
Because the flops are cascaded on a single part the metastability
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| I74F50729DB | Dual D-Type Flip-Flop |
| I74F50729D-T | Dual D-Type Flip-Flop |
| I74F50729N-B | Dual D-Type Flip-Flop |
| I74F50729D | Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
| I74F50729N | RES,FIXED,MF,243 OHM,1%,0 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| I74F50728N-B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| I74F50729D | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
| I74F50729DB | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| I74F50729D-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Dual D-Type Flip-Flop |
| I74F50729N | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Synchronizing dual D-type flip-flop with edge-triggered set and reset with metastable immune characteristics |
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