參數(shù)資料
型號： HYS72D64020GU-7-B
廠商： INFINEON TECHNOLOGIES AG
英文描述： 184-Pin Unbuffered Dual-In-Line Memory Modules
中文描述： 184引腳緩沖雙列內(nèi)存模組
文件頁數(shù)： 27/51頁
文件大?。?/td> 1356K
代理商： HYS72D64020GU-7-B
t
RPST
t
RAS
t
RC
Data Sheet
27
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
DQS falling edge to CK setup time (write
cycle)
DQS falling edge hold time from CK (write
cycle)
Mode register set command cycle time
Write preamble setup time
Write postamble
Write preamble
Address and control input setup time
t
DSS
0.2
—
0.2
—
t
CK
2)3)4)5)
t
DSH
0.2
—
0.2
—
t
CK
2)3)4)5)
t
MRD
t
WPRES
t
WPST
t
WPRE
t
IS
2
0
0.40
0.25
0.75
—
—
0.60
—
—
2
0
0.40
0.25
0.6
—
—
0.60
—
—
t
CK
ns
t
CK
t
CK
ns
2)3)4)5)
2)3)4)5)8)
2)3)4)5)9)
2)3)4)5)
fast slew rate
3)4)5)6)10)
0.8
—
NA
ns
slow slew rate
3)4)5)6)10)
Address and control input hold time
t
IH
0.75
—
0.6
—
ns
fast slew rate
3)4)5)6)10)
0.8
—
NA
ns
slow slew rate
3)4)5)6)10)
Read preamble
Read postamble
Active to Precharge command
Active to Active/Auto-refresh command
period
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Precharge command period
Active to Autoprecharge delay
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery + precharge
time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic Refresh Interval
t
RPRE
0.9
0.40
42
60
1.1
0.60
70E+3 40
—
0.9
0.40
1.1
0.60
70E+3 ns
—
t
CK
t
CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
55
ns
2)3)4)5)
t
RFC
72
—
65
—
ns
2)3)4)5)
t
RCD
t
RP
t
RAP
t
RRD
t
WR
t
DAL
18
18
18
12
15
—
—
—
—
—
15
15
15
10
15
—
—
—
—
—
ns
ns
ns
ns
ns
t
CK
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)11)
t
WTR
t
XSNR
t
XSRD
t
REFI
1
75
200
—
—
—
—
7.8
1
75
200
—
—
—
—
7.8
t
CK
ns
t
CK
μ
s
2)3)4)5)
2)3)4)5)
2)3)4)5)
2)3)4)5)12)
1) 0
°
C
≤
T
A
≤
70
°
C
; V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V (DDR333);
V
DDQ
= 2.6 V
±
0.1 V,
V
DD
= +2.6 V
±
0.1 V (DDR400)
2) Input slew rate
≥
1 V/ns for DDR400, DDR333
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Table 16
Parameter
AC Timing - Absolute Specifications –6/–5
(cont’d)
Symbol
–6
–5
Unit
Note/
Test Condition
1)
DDR333
Min.
DDR400B
Min.
Max.
Max.
相關(guān)PDF資料
PDF描述
HYS72D64020GU-7F-B RES 1.8K OHM 1/16W 5% 0402 SMD
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS72D64020GU-7F-B 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules
HYS72D64020GU-8-A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?512MB (64Mx72) PC1600 2-bank?
HYS72D64020GU-8-B 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules
HYS72D64300 制造商:QIMONDA 制造商全稱:QIMONDA 功能描述:184-Pin Registered Double Data Rate SDRAM Module
HYS72D64300GBR-5-B 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184 - Pin Registered Double Data Rate SDRAM Modules
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