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參數(shù)資料
| 型號： | HYS72D64020GR-7-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | 2.5 V 184-pin Registered DDR-I SDRAM Modules |
| 中文描述： | 2.5伏184針注冊的DDR - SDRAM內存模塊我 |
| 文件頁數(shù)： | 5/23頁 |
| 文件大小： | 418K |
| 代理商： | HYS72D64020GR-7-A |
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
INFINEON Technologies
5
2002-09-10 (revision 0.91)
Block Diagram: One Bank 32Mb x 72 DDR-I SDRAM DIMM Module
HYS72D32000GR using x8 organized SDRAMs on Raw Card Version A
PCK
PCK
D
Q
4
D
Q
5
D
Q
6
D
Q
7
D
Q
0
D
Q
1
D
Q
2
D
Q
3
DM
D0
DM0
/
D
Q
S9
D
Q
12
D
Q
13
D
Q
14
D
Q
15
D
Q
8
D
Q
9
D
Q
10
D
Q
11
DM
D1
DM1
/
D
Q
S10
D
Q
20
D
Q
21
D
Q
22
D
Q
23
D
Q
16
D
Q
17
D
Q
18
D
Q
19
DM
D2
DQ
/
D
Q
S11
D
Q
28
D
Q
29
D
Q
30
D
Q
31
D
Q
24
D
Q
25
D
Q
26
D
Q
27
DM
D3
DM3
/
D
Q
S12
D
Q
36
D
Q
37
D
Q
38
D
Q
39
D
Q
32
D
Q
33
D
Q
34
D
Q
35
DM
D4
DQ
/
D
Q
S13
D
Q
44
D
Q
45
D
Q
46
D
Q
47
D
Q
40
D
Q
41
D
Q
42
D
Q
43
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D5
DM5
/
D
Q
S14
D
Q
52
D
Q
53
D
Q
54
D
Q
55
D
Q
48
D
Q
49
D
Q
50
D
Q
51
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D6
D
Q
60
D
Q
61
D
Q
62
D
Q
63
D
Q
56
D
Q
57
D
Q
58
D
Q
59
DM
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
D7
DM7
/
D
Q
S16
Q
D
S0
CS
CS
CS
CS
CS
CS
CS
CS
D
Q
S
D
S4
D
Q
S1
D
Q
S5
D
Q
S
D
S2
D
Q
S
D
Q
S3
D
Q
S
DM6
/
D
Q
S15
D
Q
S6
D
Q
S7
CB4
CB5
CB6
CB7
CB0
CB1
CB2
CB3
DM
I
/
O 7
I
/
O 6
I
/
O 1
I
/
O 0
I
/
O 5
I
/
O 4
I
/
O 3
I
/
O 2
D8
CS
D
Q
S8
DM8
/
D
Q
S17
D
Q
S
D
Q
S
D
Q
S
D
Q
S
D
Q
S
CK0, CK 0 --------- PLL
*
*
Wire per Clock Loading Table
/
Wiring Diagrams
CS0
RS0 -
>
CS : SDRAMs D0-D8
RBA0-RBA1 -
>
BA0-BA1: SDRAMs D0-D8
BA0-BA1
A0-A12
RA0-RA12 -
>
A0-A12: SDRAMs D0 - D8
RAS
CAS
RRAS -
>
RAS : SDRAMs D0 - D8
RCAS -
>
CAS : SDRAMs D0 - D8
CKE0
WE
RCKE0 -
>
CKE: SDRAMs D0 - D8
RWE -
>
WE: SDRAMs D0 - D8
R
E
G
I
S
T
E
R
RESET
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
I
/
O 0
I
/
O 1
I
/
O 2
I
/
O 3
I
/
O 4
I
/
O 5
I
/
O 6
I
/
O 7
Notes:
1. D
Q
-to-I
/
O wiring may be changed within a byte.
2. D
Q/
D
Q
S
/
DM
/
CKE
/
S relationships must be
maintained as shown.
3. D
Q
, D
Q
S, Adress and control resistors: 22 Ohms.
4. VDDID strap connections
STRAP OUT (OPEN): VDD = VDD
Q
5. SDRAM placement alternates between the back
and front of the DIMM.
VDD,
VREF
VSS
VDDID
D0 - D8
D0 - D8
D0 - D8
VDD
Q
D0 - D8
Strap: see Note 4
VDDSPD
EEPROM
A0
Serial PD
A1
A2
SA0 SA1 SA2
SCL
SDA
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相關代理商/技術參數(shù) |
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|---|---|
| HYS72D64020GR-7-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D64020GR-8-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D64020GR-8-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D64020GU-7-A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?512MB (64Mx72) PC2100 2-bank? |
| HYS72D64020GU-7-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules |
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