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參數(shù)資料
| 型號(hào)： | HYS72D64000GR-7-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | TESTPOINT PIN RECEPTACLE |
| 中文描述： | 2.5伏184針注冊(cè)的DDR - SDRAM內(nèi)存模塊我 |
| 文件頁數(shù)： | 9/23頁 |
| 文件大?。?/td> | 418K |
| 代理商： | HYS72D64000GR-7-A |
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
INFINEON Technologies
9
2002-09-10 (revision 0.91)
Absolute Maximum Ratings
Parameter
Symbol
Limit Values
Unit
min.
max.
Input
/
Output voltage relative to V
SS
Power supply voltage on V
DD
/
V
DD
Q
to V
SS
Storage temperature range
V
IN,
V
OUT
– 0.5
3.6
V
V
DD,
V
DD
Q
– 0.5
3.6
V
T
STG
-55
+150
o
C
Power dissipation (per SDRAM component)
P
–
1
W
Data out current (short circuit)
I
OS
–
50
mA
Permanent device damage may occur if “Absolute Maximum Ratings” are exceeded.
Functional operation should be restricted to recommended operation conditions.
Exposure to higher than recommended voltage for extended periods of time affect device reliability
Supply Voltage Levels
Parameter
Symbol
Limit Values
Unit
Notes
min.
nom.
max.
Device Supply Voltage
V
DD
2.3
2.5
2.7
V
-
Output Supply Voltage
V
DD
Q
2.3
2.5
2.7
V
1)
Input Reference Voltage
V
REF
0.49 x
V
DD
Q
V
REF
– 0.04
2.3
0.5 x
V
DD
Q
0.51 x
V
DD
Q
V
REF
+ 0.04
3.6
V
2)
Termination Voltage
V
TT
V
REF
2.5
V
3)
EEPROM supply voltage
V
DDSPD
V
1 Under all conditions,
V
Q
must be less than or equal to
V
DD
2 Peak to peak AC noise on
V
may not exceed
±
2
%
V
REF (DC)
.
V
REF
is also expected to track noise variations in
V
.
3
V
TT
of the transmitting device must track
V
REF
of the receiving device.
DC Operating Conditions (SSTL_2 Inputs)
(
V
DD
Q
= 2.5 V,
T
A = 70
°
C, Voltage Referenced to
V
SS)
Parameter
Symbol
Limit Values
Unit
Notes
min.
max.
DC Input Logic High
V
IH (DC)
V
REF
+ 0.15
– 0.30
V
DD
Q
+ 0.3
V
REF
– 0.15
5
V
1)
DC Input Logic Low
V
IL (DC)
V
–
Input Leakage Current
I
IL
– 5
μ
A
μ
A
1)
Output Leakage Current
I
OL
– 5
5
2)
1) The relationship between the
V
of the driving device and the
V
of the receiving device is what
determines noise margins. However, in the case of
V
(input overdrive), it is the
V
of the receiving
device that is referenced. In the case where a device is implemented such that it supports SSTL_2 inputs but
has no SSTL_2 outputs (such as a translator), and therefore no
V
DD
Q
supply voltage connection, inputs must
tolerate input overdrive to 3.0 V (High corner
V
DD
+ 300 mV).
2) For any pin under test input of 0 V
≤
V
IN
≤
V
DD
Q
+ 0.3 V. Values are shown per DDR-SDRAM component.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS72D64000GR-7-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D64000GR-8-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D64000GR-8-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D64000GU-7-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
| HYS72D64000GU-8-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
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