HYS 72Dxx5xxGR-7F/7/8-B
Registered DDR-I SDRAM-Modules
INFINEON Technologies
11
2002-08-16 (0.91)
Operating, Standby and Refresh Currents (-7F: PC2100)
Notes
5
IDD2P
mA
2, 4
IDD2F
mA
2, 4
IDD2Q
mA
2, 4
IDD3P
mA
2, 4
IDD5
mA
1, 4
162
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
2 * n * IDDx[component]
for two bank modules (n: number of components per module bank)
3. DQ I/O (IDDQ) currents are not included into calculations: module IDD values will be measured differently
depending on load conditions
4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents
5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
for two bank modules (n: number of components per module bank)
Auto-Refresh Current
: tRC = tRFC MIN, distributed refresh
4230
MA
X
MA
X
MA
X
1620
990
1080
72
360
IDD7
IDD6
Operating Current
: four bank
;
four bank interleaving with BL=4
;
Refer to the following page for detailed test conditions.
2025
23
Self-Refresh Current
: CKE
<
= 0.2V
;
external clock on
;
tCK = tCK MIN
3240
2250
495
1035
1125
1, 3, 4
5040
4050
45
90
mA
mA
Symbol
Unit
Parameter/Condition
IDD4W
IDD4R
IDD3N
IDD1
225
144
2160
3240
3060
2, 4
648
900
288
3150
2970
1, 4
1980
Precharge Quiet Standby Current
: /CS >= VIH MIN, all banks idle
;
CKE >= VIH MIN
;
tCK = tCK MIN ,address and other control inputs stable at >=
VIH MIN or
<
= VIL MA
X;
VIN = VREF for DQ, DQS and DM.
IDD0
Operating Current
: one bank
;
active/read/precharge
;
Burst = 4
;
Refer to the following page for detailed test conditions.
Operating Current
: one bank
;
active / precharge
;
tRC = tRC MIN
;
tCK = tCK
MIN
;
DQ, DM, and DQS inputs changing once per clock cycle
;
address and
control inputs changing once every two clock cycles
Precharge Power-Down Standby Current
: all banks idle
;
power-down mode
;
CKE
<
= VIL MA
tCK = tCK MIN
Precharge Floating Standby Current
: /CS >= VIH MIN, all banks idle
;
CKE >=
VIH MIN
;
tCK = tCK MIN ,address and other control inputs changing once per
clock cycle, VIN = VREF for DQ, DQS and DM.
Active Power-Down Standby Current
: one bank active
;
power-down mode
;
CKE
<
= VIL MA
X;
tCK = tCK MIN
;
VIN = VREF for DQ, DQS and DM.
Active Standby Current
: one bank active
;
active / precharge
;
CS >= VIH MIN
;
CKE >= VIH MIN
;
tRC = tRAS MA
X;
tCK = tCK MIN
;
DQ, DM, and DQS inputs
changing twice per clock cycle
;
address and control inputs changing once per
clock cycle
: one bank active
;
Burst = 2
;
reads
;
continuous burst
;
address and control inputs changing once per clock cycle
;
50% of data outputs
changing on every clock edge
;
CL = 2 for DDR200, and DDR266A, CL=3 for
DDR333
;
tCK = tCK MIN
;
IOUT = 0mA
Operating Current
: one bank active
;
Burst = 2
;
writes
;
continuous burst
;
address and control inputs changing once per clock cycle
;
50% of data outputs
changing on every clock edge
;
CL = 2 for DDR200, and DDR266A, CL=3 for
DDR333
;
tCK = tCK MIN
1, 3, 4
2070
990
mA
1, 3, 4
2, 4
1980
mA
1440
450
mA
1, 4
256MB
x72
1bank
-7F
512MB
x72
1bank
-7F
1GB
x72
2bank
-7F
324
mA
720
mA