參數(shù)資料
型號(hào)： HYS72D128021GR-8-B
廠商： INFINEON TECHNOLOGIES AG
英文描述： Connector Wall Plate; Color:Almond; Leaded Process Compatible:Yes; No. of Ports:6 RoHS Compliant: Yes
中文描述： 2.5伏184針注冊(cè)的DDR - SDRAM內(nèi)存模塊我
文件頁(yè)數(shù)： 11/23頁(yè)
文件大小： 418K
代理商： HYS72D128021GR-8-B
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
INFINEON Technologies
11
2002-09-10 (revision 0.91)
Operating, Standby and Refresh Currents (PC2100)
Notes
5
IDD2P
mA
2, 4
IDD2F
mA
2, 4
IDD2
Q
mA
2, 4
IDD3P
mA
2, 4
IDD5
mA
1, 4
450
2115
4230
MA
X
MA
X
MA
X
MA
X
1620
900
990
72
360
162
495
1035
1125
IDD7
IDD6
Operating Current
: four bank
;
four bank interleaving with BL=4
;
Refer to the following page for detailed test conditions.
2025
27,0
Self-Refresh Current
: CKE
<
= 0.2V
;
external clock on
;
tCK = tCK MIN
Auto-Refresh Current
: tRC = tRFC MIN, distributed refresh
1, 3, 4
5040
4050
54
54
108
mA
2520
mA
Symbol
Unit
Parameter
/
Condition
IDD4W
IDD4R
IDD3N
IDD1
225
1530
1620
3240
3060
2, 4
648
900
288
2970
2790
1, 4
144
1980
1800
1395
1485
144
Precharge Quiet Standby Current
:
/
CS
>
= VIH MIN, all banks idle
;
CKE
>
= VIH MIN
;
tCK = tCK MIN ,address and other control inputs stable at
>
= VIH MIN or
<
= VIL MA
X;
VIN = VREF for D
Q
, D
Q
S and DM.
IDD0
Operating Current
: one bank
;
active
/
read
/
precharge
;
Burst = 4
;
Refer to the following page for detailed test conditions.
Operating Current
: one bank
;
active
/
precharge
;
tRC = tRC MIN
;
tCK = tCK
MIN
;
D
Q
, DM, and D
Q
S inputs changing once per clock cycle
;
address and
control inputs changing once every two clock cycles
Active Power-Down Standby Current
: one bank active
;
power-down mode
;
CKE
<
= VIL MA
X;
tCK = tCK MIN
;
VIN = VREF for D
Q
, D
Q
S and DM.
Active Standby Current
: one bank active
;
active
/
precharge
;
CS
>
= VIH
MIN
;
CKE
>
= VIH MIN
;
tRC = tRAS MA
X;
tCK = tCK MIN
;
D
Q
, DM, and D
Q
S
inputs changing twice per clock cycle
;
address and control inputs changing
once per clock cycle
Operating Current
: one bank active
;
Burst = 2
;
reads
;
continuous burst
;
address and control inputs changing once per clock cycle
;
50
%
of data
outputs changing on every clock edge
;
CL = 2 for DDR200, and DDR266A,
CL=3 for DDR333
;
tCK = tCK MIN
;
IOUT = 0mA
Operating Current
: one bank active
;
Burst = 2
;
writes
;
continuous burst
;
address and control inputs changing once per clock cycle
;
50
%
of data
outputs changing on every clock edge
;
CL = 2 for DDR200, and DDR266A,
CL=3 for DDR333
;
tCK = tCK MIN
3240
2250
2070
990
mA
1, 3, 4
2, 4
mA
720
mA
1, 3, 4
1980
mA
324
990
720
1440
450
mA
1, 4
1. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
n * IDDx[component] + n * IDD3N[component]
2. The module IDD values are calculated from the component IDD datasheet values as:
n * IDDx[component]
for single bank modules (n: number of components per module bank)
2 * n * IDDx[component]
for two bank modules (n: number of components per module bank)
3. D
Q
I
/
O (IDD
Q
) currents are not included into calculations: module IDD values will be measured differently depending on load conditions
4. DRAM component currents only: module IDD will be measured differently depending upon register and PLL operation currents
5. Test condition for maximum values: VDD = 2.7V ,Ta = 10°C
for two bank modules (n: number of components per module bank)
256MB
x72
1bank
-7
512MB
x72
1bank
-7
512MB
x72
2bank
-7
1GB
x72
2bank
-7
Precharge Power-Down Standby Current
: all banks idle
;
power-down
mode
;
CKE
<
= VIL MA
X;
tCK = tCK MIN
Precharge Floating Standby Current
:
/
CS
>
= VIH MIN, all banks idle
;
CKE
>
= VIH MIN
;
tCK = tCK MIN ,address and other control inputs changing once
per clock cycle, VIN = VREF for D
Q
, D
Q
S and DM.
324
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