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參數(shù)資料
| 型號： | HYS72D128020GR-7-A |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | CONNECTORS, PCB RoHS Compliant: Yes |
| 中文描述： | 2.5伏184針注冊的DDR - SDRAM內(nèi)存模塊我 |
| 文件頁數(shù)： | 14/23頁 |
| 文件大?。?/td> | 418K |
| 代理商： | HYS72D128020GR-7-A |
HYS 72Dxx0xxGR-7/8-B
Registered DDR-I SDRAM-Modules
INFINEON Technologies
14
2002-09-10 (revision 0.91)
t
RFC
Auto-refresh to Active
/
Auto-refresh
command period
75
80
ns
1-4
t
RCD
Active to Read or Write delay
20
20
ns
1-4
t
RP
Precharge command period
20
20
ns
1-4
t
RRD
Active bank A to Active bank B command
15
15
ns
1-4
t
WR
Write recovery time
15
15
ns
1-4
t
DAL
Auto precharge write recovery
+ precharge time
(twr
/
tck) + (trp
/
tck)
t
CK
1-4,9
t
WTR
Internal write to read command delay
1
1
t
CK
1-4
t
X
SNR
Exit self-refresh to non-read command
75
80
ns
1-4
t
X
SRD
Exit self-refresh to read command
200
200
t
CK
1-4
t
REFI
Average Periodic
Refresh Interval
256Mbit based
7.8
7.8
μ
s
1-4, 8
1. Input slew rate
>
=1V
/
ns for DDR266 and = 1V
/
ns for DDR200.
2. The CK
/
CK input reference level (for timing reference to CK
/
CK) is the point at which CK and CK cross:
the input reference level for signals other than CK
/
CK, is V
REF.
CK
/
CK slew rate are
>
= 1.0 V
/
ns.
3. Inputs are not recognized as valid until V
REF
stabilizes.
4. The Output timing reference level, as measured at the timing reference point indicated in AC Character-
istics (Note 3) is V
TT
.
5. t
and t
transitions occur in the same access time windows as valid data transitions. These parame-
ters are not referred to a specific voltage level, but specify when the device is no longer driving (H
Z
), or
begins driving (L
Z
).
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for
this parameter, but system performance (bus turnaround) degrades accordingly.
7. The specific requirement is that D
Q
S be valid (HIGH, LOW, or some point on a valid transition) on or
before this CK edge. A valid transition is defined as monotonic and meeting the input slew rate specifi-
cations of the device. When no writes were previously in progress on the bus, D
Q
S will be transitioning
from Hi-
Z
to logic LOW. If a previous write was in progress, D
Q
S could be HIGH, LOW, or transitioning
from HIGH to LOW at this time, depending on t
.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the
actual system clock cycle time.
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate
>
= 1.0 V
/
ns , slow slew rate
>
= 0.5 V
/
ns and
<
1V
/
ns for command
/
address and CK &CK
slew rate
>
1.0 V
/
ns, measured between VOH(ac) and VOL(ac)
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0
°
C
≤
T
A
≤
70
°
C
;
V
DD
Q
= 2.5V
±
0.2V
;
V
DD
= 2.5V
±
0.2V)
Symbol
Parameter
DDR266A
-7
DDR200
-8
Unit
Notes
Min
Max
Min
Max
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| HYS72D128020GR-7-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D128020GR-8-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D128020GR-8-B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Registered DDR-I SDRAM Modules |
| HYS72D128020GU-7-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
| HYS72D128020GU-8-A | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2.5 V 184-pin Unbuffered DDR-I SDRAM Modules |
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