- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄299188 > HYS64V16220GU-7.5-C (INFINEON TECHNOLOGIES AG) 16M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 PDF資料下載
參數(shù)資料
| 型號： | HYS64V16220GU-7.5-C |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | DRAM |
| 英文描述： | 16M X 64 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| 封裝： | DIM-168 |
| 文件頁數(shù)： | 3/23頁 |
| 文件大小： | 141K |
| 代理商： | HYS64V16220GU-7.5-C |
HYS 64/72V8300/16220GU
SDRAM-Modules
Data Book
11
12.99
Notes
1. These parameters depend on the cycle rate. These values are measured at 133 MHz for -7.5
modules and at 100 Mhz for -8 modules. Input signals are changed once during
t
CK, except for
I
CC6 and for standby currents when tCK = infinity. All values are shown per memory component.
2. These parameters are measured with continuous data stream during read access and all DQ
toggling. CL = 3 and BL = 4 assumed and the
V
DDQ current is excluded.
3. All AC characteristics are shown on SDRAM component level.
An initial pause of 100
s is required after power-up, then a Precharge All Banks command must
be given followed by eight Auto-Refresh (CBR) cycles before the Mode Register Set Operation
can begin.
4. AC timing tests have
V
IL = 0.4 V and VIH = 2.4 V with the timing referenced to the 1.4 V crossover
point. The transition time is measured between
V
IH and VIL. All AC measurements assume
t
T = 1 ns with the AC output load circuit show. Specified tAC and tOH parameters are measured
with a 50 pF only, without any resistive termination and with a input signal of 1 V/ns edge rate
between 0.8 V and 2.0 V.
5. If clock rising time is longer than 1 ns, a time (
t
T/2 – 0.5) ns must be added to this parameter.
6. Rated at 1.4 V
7. If
t
T is longer than 1 ns, a time (tT – 1) ns has to be added to this parameter.
8. Anytime the Refresh Period has been exceeded, a minimum of two Auto-Refresh (CBR)
commands must be given to “wake-up” the device.
9. Timing is asynchronous. If setup time is not met by rising edge of the clock then the CKE signal
is assumed latched on the next cycle.
10.Self-Refresh Exit is a synchronous operation and begins on the second positive clock edge after
CKE returns high. Self-Refresh Exit is not complete until a time period equal to
t
RC is satisfied
after the Self Refresh Exit command is registered.
11.This is referenced to the time at which the output achieves the open circuit condition, not to
output voltage levels.
A Serial Presence Detect storage device—E
2PROM—is assembled onto the module. Information
about the module configuration, speed, etc. is written into the E
2PROM device during module
production using a Serial Presence Detect protocol (I
2C synchronous 2-wire bus).
SPT03404
CLOCK
2.4 V
0.4 V
INPUT
HOLD
t
SETUP
t
T
OUTPUT
1.4 V
t
LZ
AC
t
AC
OH
t
HZ
t
1.4 V
CL
t
CH
t
50 pF
I/O
Measurement conditions for
t
AC and tOH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| HYS72T256300EP-3.7-C | 256M X 72 DDR DRAM MODULE, 0.5 ns, DMA240 |
| HYS72T64300EP-3S-B2 | 64M X 72 DDR DRAM MODULE, DMA240 |
| HYS72T64400EFD-3S-B2 | 64M X 72 DDR DRAM MODULE, DMA240 |
| HZ24H2 | 24.15 V, 0.5 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35 |
| HZ5HC2 | 5.1 V, 0.5 W, SILICON, UNIDIRECTIONAL VOLTAGE REGULATOR DIODE, DO-35 |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| HYS64V16220GU-8 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module |
| HYS64V16220GU-8B | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 8M x 64/72-Bit 1 Bank SDRAM Module 3.3 V 16M x 64/72-Bit 2 Bank SDRAM Module |
| HYS64V16300GU | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules |
| HYS64V16300GU-7.5 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x64 SDRAM Module |
| HYS64V16300GU-7.5-C2 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:3.3 V 16M x 64/72-Bit 1 Bank 128MByte SDRAM Module 3.3 V 32M x 64/72-Bit 2 Bank 256MByte SDRAM Module 168-Pin Unbuffered DIMM Modules |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。