參數(shù)資料
型號： HYS64D16301GU-8-B
廠商： INFINEON TECHNOLOGIES AG
英文描述： 184-Pin Unbuffered Dual-In-Line Memory Modules
中文描述： 184引腳緩沖雙列內(nèi)存模組
文件頁數(shù)： 25/51頁
文件大?。?/td> 1356K
代理商： HYS64D16301GU-8-B
—
Data Sheet
25
V1.1, 2003-07
HYS[64/72]D[16x01/32x00/64x20][G/E]U-[5/6/7/8]-B
Unbuffered DDR SDRAM Modules
Electrical Characteristics
Address and control input
setup time
t
IS
1.1
—
0.9
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Address and control input
hold time
t
IH
1.1
—
0.9
—
0.9
—
ns
fast slew rate
3)4)5)6)10)
1.1
—
1.0
—
1.0
—
ns
slow slew rate
3)4)5)6)10)
Read preamble
t
RPRE
t
RPRE1.5
t
RPRES
t
RPST
t
RAS
0.9
0.9
1.5
0.40
50
1.1
1.1
—
0.60
120
E+3
—
0.9
NA
NA
0.40
45
1.1
0.9
NA
NA
0.40
45
1.1
t
CK
t
CK
ns
t
CK
ns
CL > 1.5
2)3)4)5)
CL = 1.5
2)3)4)5)11)
2)3)4)5)12)
Read preamble setup time
Read postamble
Active to Precharge
command
Active to Active/Auto-
refresh command period
Auto-refresh to Active/Auto-
refresh command period
Active to Read or Write
delay
Precharge command period
t
RP
Active to Autoprecharge
delay
Active bank A to Active
bank B command
Write recovery time
Auto precharge write
recovery + precharge time
Internal write to read
command delay
0.60
120
E+3
—
0.60
120
E+3
—
2)3)4)5)
2)3)4)5)
t
RC
70
65
60
ns
2)3)4)5)
t
RFC
80
—
75
—
75
—
ns
2)3)4)5)
t
RCD
20
20
—
15
—
ns
2)3)4)5)
20
20
—
—
20
20
—
—
15
15
—
—
ns
ns
2)3)4)5)
t
RAP
2)3)4)5)
t
RRD
15
—
15
—
15
—
ns
2)3)4)5)
t
WR
t
DAL
15
—
15
(
t
wr
/
t
CK
) + (
t
rp
/
t
CK
)
—
15
—
ns
t
CK
2)3)4)5)
2)3)4)5)13)
t
WTR
t
WTR1.5
t
XSNR
1
2
80
—
—
—
1
—
75
—
—
—
1
—
75
—
—
—
t
CK
t
CK
ns
CL > 1.5
2)3)4)5)
CL = 1.5
2)3)4)5)
2)3)4)5)
Exit self-refresh to non-read
command
Exit self-refresh to read
command
Average Periodic Refresh
Interval
t
XSRD
200
—
200
—
200
—
t
CK
2)3)4)5)
t
REFI
—
7.8
—
7.8
—
7.8
μ
s
2)3)4)5)14)
1) 0
°
C
≤
T
A
≤
70
°
C;
V
DDQ
= 2.5 V
±
0.2 V,
V
DD
= +2.5 V
±
0.2 V
2) Input slew rate
≥
1 V/ns for DDR400, DDR333, DDR266, and = 1 V/ns for DDR200
3) The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
level for signals other than CK/CK, is
V
REF
. CK/CK slew rate are
≥
1.0 V/ns.
4) Inputs are not recognized as valid until
V
REF
stabilizes.
5) The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (note 3) is
V
TT
.
6) These parameters guarantee device timing, but they are not necessarily tested on each device.
Table 15
Parameter
AC Timing - Absolute Specifications –8/–7/–7F
(cont’d)
Symbol
DDR200
Min.
–8
–7
–7F
Unit
Note/
Test Condition
1)
DDR266A
Min.
DDR266
Min.
Max.
Max.
Max.
相關(guān)PDF資料
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HYS64D32000GU-8-B 184-Pin Unbuffered Dual-In-Line Memory Modules
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
HYS64D16301HU-5-C 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Double Data Rate SDRAM
HYS64D16301HU-6-C 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules
HYS64D32000GU-7-A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256MB (32Mx64) PC2100 1-bank?
HYS64D32000GU-7-B 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:184-Pin Unbuffered Dual-In-Line Memory Modules
HYS64D32000GU-8-A 制造商:未知廠家 制造商全稱:未知廠家 功能描述:?256MB (32Mx64) PC1600 1-bank End-of-Life?
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