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參數(shù)資料
| 型號： | HYR164830G-653 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 元件分類： | DRAM |
| 英文描述： | 48M X 16 RAMBUS MODULE, DMA84 |
| 封裝： | RIMM-184 |
| 文件頁數(shù)： | 12/14頁 |
| 文件大?。?/td> | 434K |
| 代理商： | HYR164830G-653 |
Last Modified on 7/13/99
Page 7
Rambus RIMM Modules
HYR16xx30G/HYR18xx20G
Table 3: Module Connector Pad Description
Signal
Module Connector Pads
I/O
Type
Description
Gnd
A1, A3, A5, A7, A9, A11, A13, A15,
A17, A19, A21, A23, A25, A27, A29,
A31, A33, A39, A52, A60, A62, A64,
A66, A68, A70, A72, A74, A76, A78,
A80, A82, A84, A86, A88, A90, A92,
B1, B3, B5, B7, B9, B11, B13, B15,
B17, B19, B21, B23, B25, B27, B29,
B31, B33, B39, B52, B60, B62, B64,
B66, B68, B70, B72, B74, B76, B78,
B80, B82, B84, B86, B88, B90, B92
Ground reference for RDRAM core and interface. 72
PCB connector pads.
LCFM
B10
IRSL
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
LCFMN
B12
IRSL
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
LCMD
B34
IVCMOS
Serial Command used to read from and write to the con-
trol registers. Also used for power management.
LCOL4..
LCOL0
A20, B20, A22, B22, A24
IRSL
Column bus. 5-bit bus containing control and address
information for column accesses.
LCTM
A14
IRSL
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Positive polarity.
LCTMN
A12
IRSL
Clock to master. Interface clock used for transmitting
RSL signals to the Channel. Negative polarity.
LDQA8..
LDQA0
A2, B2, A4, B4, A6, B6, A8, B8, A10
I/O
RSL
Data bus A. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. LDQA8 is
non-functional on modules with x16 RDRAM devices
LDQB8..
LDQB0
B32, A32, B30, A30, B28, A28, B26,
A26, B24
I/O
RSL
Data bus B. A 9-bit bus carrying a byte of read or write
data between the Channel and the RDRAM. LDQB8 is
non-functional on modules with x16 RDRAM devices.
LROW2..
LROW0
B16, A18, B18
IRSL
Row bus. 3-bit bus containing control and address infor-
mation for row accesses.
LSCK
A34
IVCMOS
Serial Clock input. Clock source used to read from and
write to the RDRAM control registers.
NC
A16, B14, A38, B38, A40, B40, A77,
B79
These pads are not connected. These 8 connector pads
are reserved for future use.
NC
A43, B43, A44, B44, A45, B45, A46,
B46, A47, B47, A48, B48, A49, B49,
A50, B50
These pads are not connected. These 16 connector pads
are reserved for future use. The 168 contact RIMM con-
nector does not connect to these PCB pads
RCFM
B83
IRSL
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Positive polarity.
RCFMN
B81
IRSL
Clock from master. Interface clock used for receiving
RSL signals from the Channel. Negative polarity.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYR166420G-653 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Direct RDRAM RIMM Modules (with 144 Mbit RDRAMs) |
| HYR166420G-745 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Direct RDRAM RIMM Modules (with 144 Mbit RDRAMs) |
| HYR166420G-840 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Direct RDRAM RIMM Modules (with 144 Mbit RDRAMs) |
| HYR166420G-845 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:Direct RDRAM RIMM Modules (with 144 Mbit RDRAMs) |
| HYR166430G-653 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:RAMBUS DRAM Module |
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