參數(shù)資料
型號(hào): HYM72V8010GS-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: Connector; Leaded Process Compatible:Yes; Peak Reflow Compatible (260 C):Yes
中文描述: 8M X 72 FAST PAGE DRAM MODULE, 50 ns, DMA168
封裝: DIMM-168
文件頁(yè)數(shù): 8/11頁(yè)
文件大?。?/td> 86K
代理商: HYM72V8010GS-50
Semiconductor Group
8
HYM72V8000/10GS-50/-60
8M x 72-ECC Module
CAS delay time from Din
t
DZC
t
DZO
t
CDD
t
ODD
0
0
ns
18
Data to OE low delay
0
0
ns
18
CAS high to data delay
18
20
ns
9,19
OE high to data delay
18
20
ns
9,19
Write Cycle
Write command hold time
t
WCH
t
WP
t
WCS
t
RWL
t
CWL
t
DS
t
DH
13
15
ns
9
Write command pulse width
8
10
ns
Write command setup time
2
2
ns
11,20
Write command to RAS lead time
18
20
ns
9
Write command to CAS lead time
13
15
ns
Data setup time
-2
-2
ns
10,21
Data hold time
15
15
ns
9,21
Read-Modify-Write Cycle
Read-write cycle time
t
RWC
t
RWD
t
CWD
t
AWD
t
OEH
131
155
ns
9
RAS to WE delay time
70
82
ns
11,21
CAS to WE delay time
33
37
ns
11,21
Column address to WE delay time
45
52
ns
11,21
OE command hold time
11
13
ns
10
Fast Page Mode Cycle
Fast page mode cycle time
t
PC
t
CP
t
CPA
t
RAS
t
RHCP
35
40
ns
CAS precharge time
10
10
ns
Access time from CAS precharge
35
40
ns
9,13
RAS pulse width
50
200k
60
200k
ns
CAS precharge to RAS Delay
35
40
ns
9
AC Characteristics
(cont’d)(note:5, 6,7,8)
T
A
= 0 to 70 °C,
V
CC
= 3.3
±
0.3 V
Parameter
Symbol
-50
-60
Unit
Note
min.
max.
min.
max.
相關(guān)PDF資料
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