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參數(shù)資料
| 型號： | HYM4V33100DTYG-75 |
| 英文描述： | x32 SDRAM Module |
| 中文描述： | X32號，內(nèi)存模塊 |
| 文件頁數(shù)： | 1/10頁 |
| 文件大?。?/td> | 73K |
| 代理商： | HYM4V33100DTYG-75 |
1Mx32 bits
PC133 SDRAM AIMM
based on 1Mx32 SDRAM with LVTTL, 2 banks & 4K Refresh
HYM4V33100BTWG Series
This document is a general product description and is subject to change without notice. Hyundai Electronics does not assume any responsibility for use of
circuits described. No patent licenses are implied.
Rev. 0.1/Apr.01
DESCRIPTION
The Hynix HYM4V33100BTWG Series are 1Mx32bits Synchronous DRAM Modules. The modules are composed of one 1Mx32bits
CMOS Synchronous DRAMs in 400mil 86pin TSOP-II package, on a 132pin glass-epoxy printed circuit board. Two 0.22uF and one
0.1uF decoupling capacitors per each SDRAM are mounted on the PCB.
The Hyundai HYM4V33100BTWG Series are AGP In-line Memory Modules suitable for easy interchange and addition of 4Mbytes
memory. The Hyundai HYM4V33100BTWG Series are fully synchronous operation referenced to the positive edge of the clock . All
inputs and outputs are synchronized with the rising edge of the clock input. The data paths are internally pipelined to achieve very high
bandwidth.
FEATURES
PC133/PC100MHz support
132pin SDRAM AIMM
1.4” (35.56mm) Height PCB with double sided com-
ponents
Single 3.3
±
0.3V power supply
All device pins are compatible with LVTTL interface
Data mask function by DQM
SDRAM internal banks : two banks
Module bank : one physical bank
Auto refresh and self refresh
4096 refresh cycles / 64ms
Programmable Burst Length and Burst Type
- 1, 2, 4 or 8 or Full page for Sequential Burst
- 1, 2, 4 or 8 for Interleave Burst
Programmable C A S Latency ; 2, 3 Clocks
ORDERING INFORMATION
Part No.
Clock
Frequency
Internal
Bank
Ref.
Power
SDRAM
Package
Plating
H Y M 4 V 3 3 1 0 0 B T W G - 7 5
133MHz
2 Banks
4 K
Normal
TSOP-II
Gold
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