參數(shù)資料
型號(hào): HYM322030S-GS50
廠商: SIEMENS AG
英文描述: 2M x 32-Bit Dynamic RAM Module
中文描述: 200萬(wàn)× 32位動(dòng)態(tài)隨機(jī)存儲(chǔ)器模塊
文件頁(yè)數(shù): 7/10頁(yè)
文件大小: 78K
代理商: HYM322030S-GS50
Semiconductor Group
7
HYM 322030S/GS-50/-60/-70
2M
×
32-Bit
AC Characteristics
5)6)
16F
T
A
= 0 to 70 °C,
V
CC
= 5 V
±
10 %,
t
T
= 5 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
-70
min.
max. min.
max. min.
max.
common parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
90
110
130
ns
RAS precharge time
30
40
50
ns
RAS pulse width
50
10k
60
10k
70
10k
ns
CAS pulse width
13
10k
15
10k
20
10k
ns
Row address setup time
0
0
0
ns
Row address hold time
8
10
10
ns
Column address setup time
0
0
0
ns
Column address hold time
10
15
15
ns
RAS to CAS delay time
18
37
20
45
20
50
RAS to column address delay
time
13
25
15
30
15
35
ns
RAS hold time
t
RSH
t
CSH
t
CRP
t
T
t
REF
13
15
20
ns
CAS hold time
50
60
70
ns
CAS to RAS precharge time
5
5
5
ns
Transition time (rise and fall)
3
50
3
50
3
50
ns
7
Refresh period
32
32
32
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
50
60
70
ns
8, 9
Access time from CAS
13
15
20
ns
8, 9
Access time from column address
t
AA
Column address to RAS lead time
t
RAL
Read command setup time
25
30
35
ns
8,10
25
30
35
ns
t
RCS
t
RCH
t
RRH
0
0
0
ns
Read command hold time
0
0
0
ns
11
Read command hold time
referenced to RAS
0
0
0
ns
11
CAS to output in low-Z
t
CLZ
t
OFF
0
0
0
ns
8
Output buffer turn-off delay
0
13
0
15
0
20
ns
12
相關(guān)PDF資料
PDF描述
HYM322030S-60 2M x 32-Bit Dynamic RAM Module
HYM322030GS-70 2M x 32-Bit Dynamic RAM Module
HYM322030S 2M x 32-Bit Dynamic RAM Module
HYM322030S-50 2M x 32-Bit Dynamic RAM Module
HYM322030S-70 2M x 32-Bit Dynamic RAM Module
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