參數(shù)資料
型號: HYM322005S
廠商: SIEMENS AG
英文描述: 2M x 32-Bit Dynamic RAM Module
中文描述: 200萬× 32位動態(tài)隨機存儲器模塊
文件頁數(shù): 7/10頁
文件大?。?/td> 85K
代理商: HYM322005S
Semiconductor Group
7
HYM 322005S/GS-50/-60
2M
×
32-Bit EDO-Module
AC Characteristics
5)6)
T
A
= 0 to 70 °C,
V
CC
= 5 V
±
10 %,
t
T
= 2 ns
Parameter
Symbol
Limit Values
-50
Unit
Note
-60
min.
max.
min.
max.
common parameters
Random read or write cycle time
t
RC
t
RP
t
RAS
t
CAS
t
ASR
t
RAH
t
ASC
t
CAH
t
RCD
t
RAD
t
RSH
t
CSH
t
CRP
t
T
t
REF
84
104
ns
RAS precharge time
30
40
ns
RAS pulse width
50
10k
60
10k
ns
CAS pulse width
8
10k
10
10k
ns
Row address setup time
0
0
ns
Row address hold time
8
10
ns
Column address setup time
0
0
ns
Column address hold time
8
10
ns
RAS to CAS delay time
12
37
14
45
ns
RAS to column address delay time
10
25
12
30
ns
RAS hold time
13
15
ns
CAS hold time
40
50
ns
CAS to RAS precharge time
5
5
ns
Transition time (rise and fall)
Refresh period
1
50
16
1
50
16
ns
ms
7
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
t
RAL
t
RCS
t
RCH
t
RRH
50
60
ns
8, 9
Access time from CAS
13
15
ns
8, 9
Access time from column address
25
30
ns
8,10
Column address to RAS lead time
25
30
ns
Read command setup time
0
0
ns
Read command hold time
0
0
ns
11
Read command hold time referenced to
RAS
0
0
ns
11
CAS to output in low-Z
t
CLZ
t
OFF
0
0
ns
8
Output buffer turn-off delay
0
13
0
15
ns
12
相關PDF資料
PDF描述
HYM322005S-50 2M x 32-Bit Dynamic RAM Module
HYM322005GS-50 2M x 32-Bit Dynamic RAM Module
HYM322005GS-60 2M x 32-Bit Dynamic RAM Module
HYM322030GS-60 2M x 32-Bit Dynamic RAM Module
HYM322030S-GS50 2M x 32-Bit Dynamic RAM Module
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