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參數(shù)資料
| 型號： | HYM322005GS-60 |
| 廠商： | SIEMENS A G |
| 元件分類： | DRAM |
| 英文描述： | 2M x 32-Bit Dynamic RAM Module |
| 中文描述： | 2M X 32 EDO DRAM MODULE, 60 ns, SMA72 |
| 封裝： | SIMM-72 |
| 文件頁數(shù)： | 9/10頁 |
| 文件大?。?/td> | 85K |
| 代理商： | HYM322005GS-60 |
Semiconductor Group
9
HYM 322005S/GS-50/-60
2M
×
32-Bit EDO-Module
Notes
1) All voltages are referenced to
V
.
Vil may undershoot to -2.0 V for pulse width of less than or equal to 4 ns. Pulse width is measured at 50%
points with amplitude measured peak to the DC reference.
2)
I
CC1
,
I
CC3
,
I
CC4
and
I
CC6
depend on cycle rate.
3)
I
CC1
and
I
CC4
depend on output loading. Specified values are obtained with the output open.
4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during
a hyper page mode (EDO) cycle.
5) An initial pause of 200
μ
s is required after power-up followed by 8 RAS cycles of which at least one cycle has
to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter,
a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required.
6) AC measurements assume
t
T
= 2 ns.
7)
V
(min.)
and
V
are reference levels for measuring timing of input signals. Transition times are also
measured between
V
I
H
and
V
I
L
.
8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined
by the latter of t
RAC
, t
CAC
, t
AA
,t
CPA
. t
CAC
is measured from tristate.
.
9) Operation within the
t
limit ensures that
t
RAC (max.)
can be met.
t
RCD (max.)
is specified as a reference point
only. If
t
RCD
is greater than the specified
t
RCD (max.)
t
CAC
.
10) Operation within the
t
)
limit ensures that
t
RAC (max.)
can be met.
t
RAD (max.)
is specified as a reference point
only. If
t
RAD
is greater than the specified
t
RAD (max.)
t
AA
.
11) Either
t
RCH
or
t
RRH
must be satisfied for a read cycle.
12)
t
define the time at which the output achieves the open-circuit conditions and are not referenced to
output voltage levels.
t
OFF
is referenced from the rising edge of RAS or CAS, whichever occurs last.
13)
t
WCS
is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only.
If
t
>
t
, the cycle is an early write cycle and data out pin will remain open-circuit (high impedance)
through the entire cycle.
14) These parameters are referenced to the CAS leading edge.
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PDF描述 |
|---|---|
| HYM322030GS-60 | 2M x 32-Bit Dynamic RAM Module |
| HYM322030S-GS50 | 2M x 32-Bit Dynamic RAM Module |
| HYM322030S-60 | 2M x 32-Bit Dynamic RAM Module |
| HYM322030GS-70 | 2M x 32-Bit Dynamic RAM Module |
| HYM322030S | 2M x 32-Bit Dynamic RAM Module |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| HYM322005S | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 32-Bit Dynamic RAM Module |
| HYM322005S-50 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 32-Bit Dynamic RAM Module |
| HYM322005S-60 | 制造商:INFINEON 制造商全稱:Infineon Technologies AG 功能描述:2M x 32-Bit Dynamic RAM Module |
| HYM32200L-60 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x(8+1) Fast Page Mode DRAM Module |
| HYM32200L-70 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:x(8+1) Fast Page Mode DRAM Module |
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