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參數(shù)資料
| 型號： | HYB39S256160TTL-5 |
| 廠商： | INFINEON TECHNOLOGIES AG |
| 英文描述： | MEMORY SPECTRUM |
| 中文描述： | 記憶譜 |
| 文件頁數(shù)： | 2/22頁 |
| 文件大?。?/td> | 564K |
| 代理商： | HYB39S256160TTL-5 |
INFINEON Technologies
10
2002-04-23
HYB39S256400/800/160DT(L)/DC(L)
256MBit Synchronous DRAM
Operation Definition
All of SDRAM operations are defined by states of control signals CS,RAS,CAS,WE,and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
Operation
Device
State
CKE
n-1
CKE
n
DQM
BA0
BA1
AP=
A10
Addr
.
CS
RAS
CAS
WE
Bank Active
Idle3
H
X
XV
VV
L
H
Bank Precharge
Any
H
X
V
L
X
L
H
L
Precharge All
Any
H
X
H
X
L
H
L
Write
Active3
HX
X
V
L
V
L
H
L
Write with Autoprecharge
Active3
H
X
XVH
V
L
H
L
Read
Active3
H
X
V
L
V
LH
Read with Autoprecharge
Active3
H
X
XVH
V
L
H
L
H
Mode Register Set
Idle
H
X
V
L
No Operation
Any
H
X
L
H
Burst Stop
Active
H
XX
X
L
H
L
Device Deselect
Any
H
XX
X
H
XX
X
Auto Refresh
Idle
H
X
L
H
Self Refresh Entry
Idle
H
L
X
L
H
Self Refresh Exit
Idle
(Self
Refr.)
L
H
XX
HX
X
L
HHX
Clock Suspend Entry
Active
H
L
X
Power Down Entry
(Precharge or active
standby)
Idle
H
L
XX
HX
X
Active4
LH
H
Clock Suspend Exit
Active
L
H
XX
Power Down Exit
Any
(Power
Down)
L
H
XX
HX
X
LH
H
L
Data Write/Output Enable
Active
H
X
L
X
Data Write/Output Disable
Active
H
X
H
X
Notes
1. V = Valid, x = Don’t Care, L = Low Level, H = High Level
2. CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the
commands are provided.
3. This is the state of the banks designated by BA0, BA1 signals.
4. Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle
device is in clock suspend mode.
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