參數(shù)資料
型號: HYB314405BJL-50
廠商: SIEMENS A G
元件分類: DRAM
英文描述: 1M x 4-Bit Dynamic RAM
中文描述: 1M X 4 EDO DRAM, 50 ns, PDSO20
封裝: 0.300 INCH, PLASTIC, SOJ-26
文件頁數(shù): 7/25頁
文件大?。?/td> 1363K
代理商: HYB314405BJL-50
Semiconductor Group
7
HYB 314405BJ/BJL-50/-60/-70
3.3V 1M x 4 EDO - DRAM
RAS hold time
t
RSH
t
CSH
t
CRP
t
T
t
REF
t
REF
13
15
17
ns
CAS hold time
50
60
70
ns
CAS to RAS precharge time
5
5
5
ns
Transition time (rise and fall)
1
50
1
50
1
50
ns
7
Refresh period
16
16
16
ms
Refresh period for L-version
128
128
128
ms
Read Cycle
Access time from RAS
t
RAC
t
CAC
t
AA
50
60
70
ns
8, 9
Access time from CAS
13
15
17
ns
8, 9
Access time from column
address
25
30
35
ns
8,10
OE access time
t
OEA
t
RAL
13
15
17
ns
Column address to RAS lead
time
25
30
35
ns
Read command setup time
t
RCS
t
RCH
t
RRH
0
0
0
ns
Read command hold time
0
0
0
ns
11
Read command hold time
referenced to RAS
0
0
0
ns
11
CAS to output in low-Z
t
CLZ
t
OFF
t
OEZ
0
0
0
ns
8
Output buffer turn-off delay
0
13
0
15
0
17
ns
12
Output buffer turn-off delay from
OE
0
13
0
15
0
17
ns
12
Data to CAS low delay
t
DZC
t
DZO
t
CDD
t
ODD
0
0
0
ns
13
Data to OE low delay
0
0
0
ns
13
CAS high to data delay
10
13
15
ns
14
OE high to data delay
10
13
15
ns
14
Write Cycle
Write command hold time
t
WCH
t
WP
8
10
10
ns
Write command pulse width
8
10
10
ns
AC Characteristics
(cont’d)
5)6)
T
A
= 0 to 70 C,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
-70
min.
max. min.
max. min.
max.
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