參數(shù)資料
型號(hào): HYB314405BJBJL-50-
廠商: SIEMENS AG
英文描述: 1M x 4-Bit Dynamic RAM
中文描述: 100萬(wàn)× 4位動(dòng)態(tài)隨機(jī)存儲(chǔ)器
文件頁(yè)數(shù): 9/25頁(yè)
文件大?。?/td> 1363K
代理商: HYB314405BJBJL-50-
Semiconductor Group
9
HYB 314405BJ/BJL-50/-60/-70
3.3V 1M x 4 EDO - DRAM
CAS before RAS Refresh Cycle
CAS setup time
t
CSR
t
CHR
t
RPC
t
WRP
t
WRH
10
10
10
ns
CAS hold time
10
10
10
ns
RAS to CAS precharge time
5
5
5
ns
Write to RAS precharge time
10
10
10
ns
Write hold time referenced to
RAS
10
10
10
ns
CAS-before-RAS Counter Test Cycle
CAS precharge time (CAS-
before-RAS counter test cycle)
t
CPT
35
40
40
ns
Test Mode
Write command setup time
t
WTS
t
WTH
10
10
10
ns
Write command hold time
10
10
10
ns
Capacitance
T
A
= 0 to 70 C;
V
CC
= 3.3 V
±
0.3 V;
f
= 1 MHz
Parameter
Symbol
Limit Values
Unit
min.
max.
Input capacitance (A0 to A9)
C
I1
C
I2
C
I0
5
pF
Input capacitance (RAS, CAS, WE,OE)
7
pF
Output capacitance (IO1 to IO4)
7
pF
AC Characteristics
(cont’d)
5)6)
T
A
= 0 to 70 C,
V
CC
= 3.3 V
±
0.3 V,
t
T
= 2 ns
Parameter
Symbol
Limit Values
Unit
Note
-50
-60
-70
min.
max. min.
max. min.
max.
相關(guān)PDF資料
PDF描述
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